{"id":2233287,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2233287/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260506033642.3641390-4-jim.shu@sifive.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260506033642.3641390-4-jim.shu@sifive.com>","list_archive_url":null,"date":"2026-05-06T03:36:40","name":"[v3,3/5] accel/tcg: Provide early AS translate function","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"2123eacf94c179185d82cd1160cb2b64d737cee4","submitter":{"id":83153,"url":"http://patchwork.ozlabs.org/api/1.2/people/83153/?format=json","name":"Jim Shu","email":"jim.shu@sifive.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260506033642.3641390-4-jim.shu@sifive.com/mbox/","series":[{"id":502923,"url":"http://patchwork.ozlabs.org/api/1.2/series/502923/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502923","date":"2026-05-06T03:36:39","name":"Defer the IOMMU translation in the CPU path and support access_type","version":3,"mbox":"http://patchwork.ozlabs.org/series/502923/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2233287/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2233287/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=sifive.com header.i=@sifive.com header.a=rsa-sha256\n header.s=google header.b=LcS/rs5F;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Iglesias\" ,\n Aurelien Jarno , Jiaxun Yang ,\n Aleksandar Rikalo , Stafford Horne ,\n Nicholas Piggin , Chinmay Rath ,\n Glenn Miles , Palmer Dabbelt ,\n Alistair Francis , Weiwei Li ,\n Daniel Henrique Barboza ,\n Liu Zhiwei ,\n Chao Liu ,\n Yoshinori Sato ,\n Ilya Leoshkevich , David Hildenbrand ,\n Cornelia Huck , Eric Farman ,\n Matthew Rosato ,\n Mark Cave-Ayland ,\n Artyom Tarasenko , Max Filippov ,\n qemu-ppc@nongnu.org (open list:PowerPC TCG CPUs),\n qemu-s390x@nongnu.org (open list:S390 TCG CPUs),\n Pierrick Bouvier ,\n Mark Burton ,\n Peter Maydell , Jim Shu ","Subject":"[PATCH v3 3/5] accel/tcg: Provide early AS translate function","Date":"Wed, 6 May 2026 11:36:40 +0800","Message-ID":"<20260506033642.3641390-4-jim.shu@sifive.com>","X-Mailer":"git-send-email 2.43.0","In-Reply-To":"<20260506033642.3641390-1-jim.shu@sifive.com>","References":"<20260506033642.3641390-1-jim.shu@sifive.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2607:f8b0:4864:20::629;\n envelope-from=jim.shu@sifive.com; helo=mail-pl1-x629.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"New early AS translate function will skip IOMMU translation. It will\nreturn IOMMU region if finding it. Original function is renamed to the\nlate translate function.\n\nIt is preparation commit of IOMMU lazy translation.\n\nSigned-off-by: Jim Shu \nAcked-by: Pierrick Bouvier \n---\n accel/tcg/cputlb.c | 6 ++---\n include/accel/tcg/iommu.h | 13 +++++++----\n system/physmem.c | 46 ++++++++++++++++++++++++++++++++++++---\n 3 files changed, 55 insertions(+), 10 deletions(-)","diff":"diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c\nindex 4ca4152579b..f0c049e1551 100644\n--- a/accel/tcg/cputlb.c\n+++ b/accel/tcg/cputlb.c\n@@ -1049,9 +1049,9 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx,\n \n prot = full->prot;\n asidx = cpu_asidx_from_attrs(cpu, full->attrs);\n- section = address_space_translate_for_iotlb(cpu, asidx, paddr_page,\n- &xlat, &sz, full->attrs, &prot,\n- access_type);\n+ section = address_space_translate_for_iotlb_late(cpu, asidx, paddr_page,\n+ &xlat, &sz, full->attrs,\n+ &prot);\n assert(sz >= TARGET_PAGE_SIZE);\n \n tlb_debug(\"vaddr=%016\" VADDR_PRIx \" paddr=0x\" HWADDR_FMT_plx\ndiff --git a/include/accel/tcg/iommu.h b/include/accel/tcg/iommu.h\nindex 30655aab4ba..11e3d63d798 100644\n--- a/include/accel/tcg/iommu.h\n+++ b/include/accel/tcg/iommu.h\n@@ -15,10 +15,15 @@\n #include \"exec/memattrs.h\"\n \n MemoryRegionSection *\n-address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr,\n- hwaddr *xlat, hwaddr *plen,\n- MemTxAttrs attrs, int *prot,\n- MMUAccessType access_type);\n+address_space_translate_for_iotlb_early(CPUState *cpu, int asidx, hwaddr addr,\n+ hwaddr *xlat, hwaddr *plen,\n+ MemTxAttrs attrs, int *prot);\n+\n+MemoryRegionSection *\n+address_space_translate_for_iotlb_late(CPUState *cpu, int asidx, hwaddr addr,\n+ hwaddr *xlat, hwaddr *plen,\n+ MemTxAttrs attrs, int *prot,\n+ MMUAccessType access_type);\n \n #endif\n \ndiff --git a/system/physmem.c b/system/physmem.c\nindex 564d2c6a648..6e2d43e850f 100644\n--- a/system/physmem.c\n+++ b/system/physmem.c\n@@ -682,11 +682,11 @@ void tcg_iommu_init_notifier_list(CPUState *cpu)\n }\n \n /* Called from RCU critical section */\n-MemoryRegionSection *\n+static MemoryRegionSection *\n address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr orig_addr,\n hwaddr *xlat, hwaddr *plen,\n MemTxAttrs attrs, int *prot,\n- MMUAccessType access_type)\n+ MMUAccessType access_type, bool early_trans)\n {\n MemoryRegionSection *section;\n IOMMUMemoryRegion *iommu_mr;\n@@ -710,6 +710,11 @@ address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr orig_addr,\n iommu_idx = imrc->attrs_to_index(iommu_mr, attrs);\n tcg_register_iommu_notifier(cpu, iommu_mr, iommu_idx);\n \n+ /* Defer the iommu translation */\n+ if (early_trans) {\n+ break;\n+ }\n+\n if (access_type == MMU_DATA_STORE) {\n iommu_flags = IOMMU_WO;\n } else {\n@@ -737,7 +742,8 @@ address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr orig_addr,\n d = flatview_to_dispatch(address_space_to_flatview(iotlb.target_as));\n }\n \n- assert(!memory_region_is_iommu(section->mr));\n+ /* For late translation, IOMMU region translation should be finished */\n+ assert(early_trans || !memory_region_is_iommu(section->mr));\n *xlat = addr;\n return section;\n \n@@ -755,6 +761,40 @@ translate_fail:\n return &d->map.sections[PHYS_SECTION_UNASSIGNED];\n }\n \n+/*\n+ * address_space_translate_for_iotlb_early: translate address without\n+ * performing IOMMU translation. This is used for CPU TLB setup.\n+ *\n+ * Called from RCU critical section.\n+ */\n+MemoryRegionSection *\n+address_space_translate_for_iotlb_early(CPUState *cpu, int asidx,\n+ hwaddr orig_addr,\n+ hwaddr *xlat, hwaddr *plen,\n+ MemTxAttrs attrs, int *prot)\n+{\n+ /* access_type doesn't matter for early translation */\n+ return address_space_translate_for_iotlb(cpu, asidx, orig_addr, xlat, plen,\n+ attrs, prot, MMU_DATA_LOAD, true);\n+}\n+\n+/*\n+ * address_space_translate_for_iotlb_late: translate address with\n+ * performing IOMMU translation. This is used for lazy IOMMU translation.\n+ *\n+ * Called from RCU critical section.\n+ */\n+MemoryRegionSection *\n+address_space_translate_for_iotlb_late(CPUState *cpu, int asidx,\n+ hwaddr orig_addr,\n+ hwaddr *xlat, hwaddr *plen,\n+ MemTxAttrs attrs, int *prot,\n+ MMUAccessType access_type)\n+{\n+ return address_space_translate_for_iotlb(cpu, asidx, orig_addr, xlat, plen,\n+ attrs, prot, access_type, false);\n+}\n+\n #endif /* CONFIG_TCG */\n \n void cpu_address_space_init(CPUState *cpu, int asidx,\n","prefixes":["v3","3/5"]}