{"id":2233147,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2233147/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260505185028.237207-4-dblanzeanu@linux.microsoft.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260505185028.237207-4-dblanzeanu@linux.microsoft.com>","list_archive_url":null,"date":"2026-05-05T18:50:24","name":"[v2,3/7] include/hw/hyperv: add hv_vp_register_page struct definition","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"b903ac2414b172e2fcc377c873605e51266cba43","submitter":{"id":93106,"url":"http://patchwork.ozlabs.org/api/1.2/people/93106/?format=json","name":"Doru Blânzeanu","email":"dblanzeanu@linux.microsoft.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260505185028.237207-4-dblanzeanu@linux.microsoft.com/mbox/","series":[{"id":502882,"url":"http://patchwork.ozlabs.org/api/1.2/series/502882/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502882","date":"2026-05-05T18:50:22","name":"target/i386/mshv: use hv_vp_register_page for fast register access","version":2,"mbox":"http://patchwork.ozlabs.org/series/502882/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2233147/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2233147/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=linux.microsoft.com header.i=@linux.microsoft.com\n header.a=rsa-sha256 header.s=default header.b=UgCal4l4;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g970d32ltz1yJx\n\tfor ; Wed, 06 May 2026 04:52:01 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wKKr6-0000g0-FI; Tue, 05 May 2026 14:50:52 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wKKr2-0000eg-5C\n for qemu-devel@nongnu.org; Tue, 05 May 2026 14:50:48 -0400","from linux.microsoft.com ([13.77.154.182])\n by eggs.gnu.org with esmtp (Exim 4.90_1)\n (envelope-from ) id 1wKKqx-0006in-57\n for qemu-devel@nongnu.org; Tue, 05 May 2026 14:50:44 -0400","from laptop.localdomain (unknown [86.121.140.248])\n by linux.microsoft.com (Postfix) with ESMTPSA id 745AB20B716B;\n Tue, 5 May 2026 11:50:38 -0700 (PDT)"],"DKIM-Filter":"OpenDKIM Filter v2.11.0 linux.microsoft.com 745AB20B716B","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com;\n s=default; t=1778007040;\n bh=JoVfvivCSpq5Fgy432g9+gtjWSn5QfgpvK1DLQ5a2J0=;\n h=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n b=UgCal4l4oMIEHjyQpS4F4dwsq45xDLz65BLBqzsJkKqrB0K1GABQh1rAnPRgcO7xh\n oEHm5CXovPBSDjYgSJR+FDFdH/X/dhs0xoZK8NHxYQn/tfYC+qYjOT6BGiOdWEJiVj\n 4pxtYQJ7Y62PhJLG2JTtnqRTFZx8rR/nhf5az1ZU=","From":"=?utf-8?q?Doru_Bl=C3=A2nzeanu?= ","To":"qemu-devel@nongnu.org","Cc":"=?utf-8?q?Doru_Bl=C3=A2nzeanu?= ,\n Magnus Kulke ,\n Zhao Liu , Wei Liu ,\n Paolo Bonzini ","Subject":"[PATCH v2 3/7] include/hw/hyperv: add hv_vp_register_page struct\n definition","Date":"Tue, 5 May 2026 21:50:24 +0300","Message-ID":"<20260505185028.237207-4-dblanzeanu@linux.microsoft.com>","X-Mailer":"git-send-email 2.53.0","In-Reply-To":"<20260505185028.237207-1-dblanzeanu@linux.microsoft.com>","References":"<20260505185028.237207-1-dblanzeanu@linux.microsoft.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=UTF-8","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=13.77.154.182;\n envelope-from=dblanzeanu@linux.microsoft.com; helo=linux.microsoft.com","X-Spam_score_int":"-19","X-Spam_score":"-2.0","X-Spam_bar":"--","X-Spam_report":"(-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, RCVD_IN_DNSWL_NONE=-0.0001,\n SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Define the `hv_vp_register_page` structure that the linux kernel uses\nto allow access to vcpu registers.\n\nThis structure is going to be used in later patches to access vcpu\nregisters.\n\nSigned-off-by: Doru Blânzeanu \n---\n include/hw/hyperv/hvgdk.h | 2 +\n include/hw/hyperv/hvhdk.h | 105 ++++++++++++++++++++++++++++++++++++++\n 2 files changed, 107 insertions(+)","diff":"diff --git a/include/hw/hyperv/hvgdk.h b/include/hw/hyperv/hvgdk.h\nindex 71161f477c..e4be861716 100644\n--- a/include/hw/hyperv/hvgdk.h\n+++ b/include/hw/hyperv/hvgdk.h\n@@ -9,6 +9,8 @@\n #ifndef HW_HYPERV_HVGDK_H\n #define HW_HYPERV_HVGDK_H\n \n+#include \"hvgdk_mini.h\"\n+\n #define HVGDK_H_VERSION (25125)\n \n enum hv_unimplemented_msr_action {\ndiff --git a/include/hw/hyperv/hvhdk.h b/include/hw/hyperv/hvhdk.h\nindex 41af743847..4a3b543893 100644\n--- a/include/hw/hyperv/hvhdk.h\n+++ b/include/hw/hyperv/hvhdk.h\n@@ -9,7 +9,11 @@\n #ifndef HW_HYPERV_HVHDK_H\n #define HW_HYPERV_HVHDK_H\n \n+#include \"hvgdk.h\"\n+#include \"hvhdk_mini.h\"\n+\n #define HV_PARTITION_SYNTHETIC_PROCESSOR_FEATURES_BANKS 1\n+#define HV_VP_REGISTER_PAGE_MAX_VECTOR_COUNT 7\n \n struct hv_input_set_partition_property {\n uint64_t partition_id;\n@@ -246,4 +250,105 @@ typedef struct hv_input_register_intercept_result {\n union hv_register_intercept_result_parameters parameters;\n } QEMU_PACKED hv_input_register_intercept_result;\n \n+/* Flags for dirty mask of hv_vp_register_page */\n+enum hv_x64_register_class_type {\n+ HV_X64_REGISTER_CLASS_GENERAL = 0,\n+ HV_X64_REGISTER_CLASS_IP = 1,\n+ HV_X64_REGISTER_CLASS_XMM = 2,\n+ HV_X64_REGISTER_CLASS_SEGMENT = 3,\n+ HV_X64_REGISTER_CLASS_FLAGS = 4,\n+};\n+\n+union hv_vp_register_page_interrupt_vectors {\n+ uint64_t as_uint64;\n+ struct {\n+ uint8_t vector_count;\n+ uint8_t vector[HV_VP_REGISTER_PAGE_MAX_VECTOR_COUNT];\n+ };\n+};\n+\n+struct hv_vp_register_page {\n+ uint16_t version;\n+ uint8_t isvalid;\n+ uint8_t rsvdz;\n+ uint32_t dirty;\n+\n+ union {\n+ struct {\n+ /* General purpose registers (HV_X64_REGISTER_CLASS_GENERAL) */\n+ union {\n+ struct {\n+ uint64_t rax;\n+ uint64_t rcx;\n+ uint64_t rdx;\n+ uint64_t rbx;\n+ uint64_t rsp;\n+ uint64_t rbp;\n+ uint64_t rsi;\n+ uint64_t rdi;\n+ uint64_t r8;\n+ uint64_t r9;\n+ uint64_t r10;\n+ uint64_t r11;\n+ uint64_t r12;\n+ uint64_t r13;\n+ uint64_t r14;\n+ uint64_t r15;\n+ } QEMU_PACKED;\n+\n+ uint64_t gp_registers[16];\n+ };\n+ /* Instruction pointer (HV_X64_REGISTER_CLASS_IP) */\n+ uint64_t rip;\n+ /* Flags (HV_X64_REGISTER_CLASS_FLAGS) */\n+ uint64_t rflags;\n+ } QEMU_PACKED;\n+\n+ uint64_t registers[18];\n+ };\n+ uint8_t reserved[8];\n+ /* Volatile XMM registers (HV_X64_REGISTER_CLASS_XMM) */\n+ union {\n+ struct {\n+ struct hv_u128 xmm0;\n+ struct hv_u128 xmm1;\n+ struct hv_u128 xmm2;\n+ struct hv_u128 xmm3;\n+ struct hv_u128 xmm4;\n+ struct hv_u128 xmm5;\n+ } QEMU_PACKED;\n+\n+ struct hv_u128 xmm_registers[6];\n+ };\n+ /* Segment registers (HV_X64_REGISTER_CLASS_SEGMENT) */\n+ union {\n+ struct {\n+ struct hv_x64_segment_register es;\n+ struct hv_x64_segment_register cs;\n+ struct hv_x64_segment_register ss;\n+ struct hv_x64_segment_register ds;\n+ struct hv_x64_segment_register fs;\n+ struct hv_x64_segment_register gs;\n+ } QEMU_PACKED;\n+\n+ struct hv_x64_segment_register segment_registers[6];\n+ };\n+ /* Misc. control registers (cannot be set via this interface) */\n+ uint64_t cr0;\n+ uint64_t cr3;\n+ uint64_t cr4;\n+ uint64_t cr8;\n+ uint64_t efer;\n+ uint64_t dr7;\n+ union hv_x64_pending_interruption_register pending_interruption;\n+ union hv_x64_interrupt_state_register interrupt_state;\n+ uint64_t instruction_emulation_hints;\n+ uint64_t xfem;\n+\n+ uint8_t reserved1[0x100];\n+\n+ /* Interrupts injected as part of HvCallDispatchVp. */\n+ union hv_vp_register_page_interrupt_vectors interrupt_vectors;\n+} QEMU_PACKED;\n+\n #endif /* HW_HYPERV_HVHDK_H */\n","prefixes":["v2","3/7"]}