{"id":2233142,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2233142/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260505185028.237207-7-dblanzeanu@linux.microsoft.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260505185028.237207-7-dblanzeanu@linux.microsoft.com>","list_archive_url":null,"date":"2026-05-05T18:50:27","name":"[v2,6/7] target/i386/mshv: use the register page to set registers","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"a780126a45fd96f9faa826ca4fedbcf5a03fd7ab","submitter":{"id":93106,"url":"http://patchwork.ozlabs.org/api/1.2/people/93106/?format=json","name":"Doru Blânzeanu","email":"dblanzeanu@linux.microsoft.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260505185028.237207-7-dblanzeanu@linux.microsoft.com/mbox/","series":[{"id":502882,"url":"http://patchwork.ozlabs.org/api/1.2/series/502882/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502882","date":"2026-05-05T18:50:22","name":"target/i386/mshv: use hv_vp_register_page for fast register access","version":2,"mbox":"http://patchwork.ozlabs.org/series/502882/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2233142/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2233142/checks/","tags":{},"related":[],"headers":{"Return-Path":"<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=linux.microsoft.com header.i=@linux.microsoft.com\n header.a=rsa-sha256 header.s=default header.b=KgpnVCSX;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=13.77.154.182;\n envelope-from=dblanzeanu@linux.microsoft.com; helo=linux.microsoft.com","X-Spam_score_int":"-19","X-Spam_score":"-2.0","X-Spam_bar":"--","X-Spam_report":"(-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, RCVD_IN_DNSWL_NONE=-0.0001,\n SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development <qemu-devel.nongnu.org>","List-Unsubscribe":"<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>","List-Archive":"<https://lists.nongnu.org/archive/html/qemu-devel>","List-Post":"<mailto:qemu-devel@nongnu.org>","List-Help":"<mailto:qemu-devel-request@nongnu.org?subject=help>","List-Subscribe":"<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Update mshv_store_regs to use the register page when it is mmapped and\nvalid to set registers.\nOtherwise use the ioctls to set the registers.\n\nSigned-off-by: Doru Blânzeanu <dblanzeanu@linux.microsoft.com>\n---\n target/i386/mshv/mshv-cpu.c | 45 +++++++++++++++++++++++++++++++++----\n 1 file changed, 41 insertions(+), 4 deletions(-)","diff":"diff --git a/target/i386/mshv/mshv-cpu.c b/target/i386/mshv/mshv-cpu.c\nindex c84d3f76de..0cfac26a5c 100644\n--- a/target/i386/mshv/mshv-cpu.c\n+++ b/target/i386/mshv/mshv-cpu.c\n@@ -285,14 +285,51 @@ static int set_standard_regs(const CPUState *cpu)\n     return 0;\n }\n \n+static void mshv_set_standard_regs_vp_page(CPUState *cpu)\n+{\n+    X86CPU *x86cpu = X86_CPU(cpu);\n+    CPUX86State *env = &x86cpu->env;\n+\n+    env->regs_page->rax = env->regs[R_EAX];\n+    env->regs_page->rbx = env->regs[R_EBX];\n+    env->regs_page->rcx = env->regs[R_ECX];\n+    env->regs_page->rdx = env->regs[R_EDX];\n+    env->regs_page->rsi = env->regs[R_ESI];\n+    env->regs_page->rdi = env->regs[R_EDI];\n+    env->regs_page->rsp = env->regs[R_ESP];\n+    env->regs_page->rbp = env->regs[R_EBP];\n+    env->regs_page->r8  = env->regs[R_R8];\n+    env->regs_page->r9  = env->regs[R_R9];\n+    env->regs_page->r10 = env->regs[R_R10];\n+    env->regs_page->r11 = env->regs[R_R11];\n+    env->regs_page->r12 = env->regs[R_R12];\n+    env->regs_page->r13 = env->regs[R_R13];\n+    env->regs_page->r14 = env->regs[R_R14];\n+    env->regs_page->r15 = env->regs[R_R15];\n+    env->regs_page->rip = env->eip;\n+    lflags_to_rflags(env);\n+    env->regs_page->rflags = env->eflags;\n+\n+    env->regs_page->dirty |= (1u << HV_X64_REGISTER_CLASS_GENERAL)\n+                                | (1u << HV_X64_REGISTER_CLASS_IP)\n+                                | (1u << HV_X64_REGISTER_CLASS_FLAGS);\n+}\n+\n int mshv_store_regs(CPUState *cpu)\n {\n+    X86CPU *x86cpu = X86_CPU(cpu);\n+    CPUX86State *env = &x86cpu->env;\n     int ret;\n \n-    ret = set_standard_regs(cpu);\n-    if (ret < 0) {\n-        error_report(\"Failed to store standard registers\");\n-        return -1;\n+    /* Use register vp page to optimize registers access */\n+    if (env->regs_page && env->regs_page->isvalid != 0) {\n+        mshv_set_standard_regs_vp_page(cpu);\n+    } else {\n+        ret = set_standard_regs(cpu);\n+        if (ret < 0) {\n+            error_report(\"Failed to store standard registers\");\n+            return -1;\n+        }\n     }\n \n     return 0;\n","prefixes":["v2","6/7"]}