{"id":2232990,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2232990/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/b29f473500bb3214a7d44495c12e4f152928b6ba.1777984225.git.michal.simek@amd.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/1.2/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"","list_archive_url":null,"date":"2026-05-05T12:30:31","name":"[v2,3/4] spi: cadence: Use reset_reset_bulk() for proper reset cycling","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"7a801e0fa68f6fc1c58d21ab836c05d6df307b89","submitter":{"id":84271,"url":"http://patchwork.ozlabs.org/api/1.2/people/84271/?format=json","name":"Michal Simek","email":"michal.simek@amd.com"},"delegate":{"id":3651,"url":"http://patchwork.ozlabs.org/api/1.2/users/3651/?format=json","username":"trini","first_name":"Tom","last_name":"Rini","email":"trini@ti.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/b29f473500bb3214a7d44495c12e4f152928b6ba.1777984225.git.michal.simek@amd.com/mbox/","series":[{"id":502832,"url":"http://patchwork.ozlabs.org/api/1.2/series/502832/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=502832","date":"2026-05-05T12:30:28","name":"reset: Introduce reset_reset.*() API","version":2,"mbox":"http://patchwork.ozlabs.org/series/502832/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2232990/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2232990/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=amd.com header.i=@amd.com header.a=rsa-sha256\n header.s=selector1 header.b=SIj+77P9;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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helo=satlexmb08.amd.com; pr=C","None (SATLEXMB03.amd.com: michal.simek@amd.com does not\n designate permitted sender hosts)"],"From":"Michal Simek ","To":", , Simon Glass ","CC":"Andrew Goodbody , Naman Trivedi\n , Padmarao Begari ,\n Tom Rini , Venkatesh Yadav Abbarapu\n ","Subject":"[PATCH v2 3/4] spi: cadence: Use reset_reset_bulk() for proper reset\n cycling","Date":"Tue, 5 May 2026 14:30:31 +0200","Message-ID":"\n ","X-Mailer":"git-send-email 2.43.0","In-Reply-To":"","References":"","MIME-Version":"1.0","X-Developer-Signature":"v=1; a=openpgp-sha256; l=1545; i=michal.simek@amd.com;\n h=from:subject:message-id; bh=UnrD+ml8QGmKddaN8sLah81igDE0WNiYefrozswG1Ys=;\n b=owGbwMvMwCG2mv3fB7+vgl8ZT6slMWT+fPR6S4NRtfFitlD54jNXa65PD9I8esN5TyFnnf8RK\n 8vTevK3O0pZGMQ4GGTFFFmmM+k4rPl2banY8sh8mDmsTCBDGLg4BeAmL2T4Z7H7x9dO546dOh8q\n rzHKHlFjzXdP904ujDvic9CBw2GbHCPDc6mXxaIRO4TNim7uXpxilW56NmW+epzWjwn3a6IX7vn\n OAAA=","X-Developer-Key":"i=michal.simek@amd.com; a=openpgp;\n fpr=67350C9BF5CCEE9B5364356A377C7F21FE3D1F91","Content-Transfer-Encoding":"8bit","Content-Type":"text/plain","X-EOPAttributedMessage":"0","X-MS-PublicTrafficType":"Email","X-MS-TrafficTypeDiagnostic":"CH1PEPF0000AD77:EE_|DSSPR12MB999237:EE_","X-MS-Office365-Filtering-Correlation-Id":"29b581e1-ab05-4e89-682d-08deaaa226d2","X-MS-Exchange-SenderADCheck":"1","X-MS-Exchange-AntiSpam-Relay":"0","X-Microsoft-Antispam":"BCL:0;\n ARA:13230040|1800799024|376014|82310400026|36860700016|56012099003|22082099003|18002099003;","X-Microsoft-Antispam-Message-Info":"\n I9E4B+4V7e9ihYQI19sKZfA9w9J8/Km2OlYMSbsw6dKSUEa/BsFwrINbRmQvGlmiIskSdtBUM0QAphR+VfyKX3ngm2Xhxfj/h3dqDUfrFi8V4UH/0MtRvPwJDdE/hqi9Wdi/L4X0Tec/4+jDV7STWnIfqUSeLZu3p3oNmq4eKocGa0DkaAI2idcGAtp6jbuwjyv+PMcjA8GzDtjYzz7OKhfjaCtZPeWAX6eScSlFLzNIvj9Qm2/Goukrs9G9NA+DfMyufeOjnQQSv59O2EYn93wI+9W1kpUt3fISXY56j7JHlcmfVJgpDZnEVRGOdjU7t5Z2CJ0x01e4o0wI9/VJYeoyliTS/nLHJuQ8Exyu3wpTCTBQtBT1AiN8yCIMntO4OguAA6UXRByuxZGTb3dW/9ksOE/vPLJg/fT/PKMe2z2RxmCykfihTqZwptk0mQNSxoTARzUTzYN7mOy83HMZHiz2aQbYEv7wjbEhQv42EIbcsqFtYh3gniR8ZJwfEFypjRffx1mgb2436+8X6dB6XJP60HC0s44RVNeXBSbP64GA0arru/GsU8ECsgp29ZnbiZh/ZvvPvaOTZSt1myzBFE5PwJlEEASODmLcBYF67DnFkJMwil7gx+tdrSqLSxPkRyZzfxI8jmItC8uRqP7mKQRi2wKcBQDRNz/FZUrLvVAj9ytbxCQR1axLAS6UQwwoqzvhRbp7kQtTSB7vP7QI5lXcJbLJGUXCrbv69q7Sshs=","X-Forefront-Antispam-Report":"CIP:165.204.84.17; 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Ip=[165.204.84.17];\n Helo=[satlexmb08.amd.com]","X-MS-Exchange-CrossTenant-AuthSource":"\n CH1PEPF0000AD77.namprd04.prod.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Anonymous","X-MS-Exchange-CrossTenant-FromEntityHeader":"HybridOnPrem","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"DSSPR12MB999237","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.39","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" ","X-Virus-Scanned":"clamav-milter 0.103.8 at phobos.denx.de","X-Virus-Status":"Clean"},"content":"Use the new reset_reset_bulk() API to properly cycle reset signals\nduring probe instead of just deasserting them. This ensures the\ncontroller is properly reset before initialization.\n\nSigned-off-by: Michal Simek \nReviewed-by: Simon Glass \n---\n\nChanges in v2:\n- Pass 10us via parameter\n\n drivers/spi/cadence_qspi.c | 16 ++++------------\n 1 file changed, 4 insertions(+), 12 deletions(-)","diff":"diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c\nindex 2a4a49c5f1cf..984d4a39ded4 100644\n--- a/drivers/spi/cadence_qspi.c\n+++ b/drivers/spi/cadence_qspi.c\n@@ -31,6 +31,8 @@\n #define CQSPI_DISABLE_STIG_MODE\t\tBIT(0)\n #define CQSPI_DMA_MODE\t\t\tBIT(1)\n \n+#define CQSPI_RESET_DELAY_US\t\t10\n+\n __weak int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv,\n \t\t\t\t const struct spi_mem_op *op)\n {\n@@ -256,19 +258,9 @@ static int cadence_spi_probe(struct udevice *bus)\n \n \tpriv->resets = devm_reset_bulk_get_optional(bus);\n \tif (priv->resets) {\n-\t\t/* Assert all OSPI reset lines */\n-\t\tret = reset_assert_bulk(priv->resets);\n-\t\tif (ret) {\n-\t\t\tdev_err(bus, \"Failed to assert OSPI reset: %d\\n\", ret);\n-\t\t\treturn ret;\n-\t\t}\n-\n-\t\tudelay(10);\n-\n-\t\t/* Deassert all OSPI reset lines */\n-\t\tret = reset_deassert_bulk(priv->resets);\n+\t\tret = reset_reset_bulk(priv->resets, CQSPI_RESET_DELAY_US);\n \t\tif (ret) {\n-\t\t\tdev_err(bus, \"Failed to deassert OSPI reset: %d\\n\", ret);\n+\t\t\tdev_err(bus, \"Failed to reset OSPI: %d\\n\", ret);\n \t\t\treturn ret;\n \t\t}\n \t}\n","prefixes":["v2","3/4"]}