{"id":2232958,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2232958/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-tegra/patch/20260505105928.38457-3-akhilrajeev@nvidia.com/","project":{"id":21,"url":"http://patchwork.ozlabs.org/api/1.2/projects/21/?format=json","name":"Linux Tegra Development","link_name":"linux-tegra","list_id":"linux-tegra.vger.kernel.org","list_email":"linux-tegra@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260505105928.38457-3-akhilrajeev@nvidia.com>","list_archive_url":null,"date":"2026-05-05T10:59:26","name":"[2/4] i2c: tegra: Disable fair arbitration for non-MCTP buses","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"f12047435ce35de794e1972074eda3fff7c7d538","submitter":{"id":81965,"url":"http://patchwork.ozlabs.org/api/1.2/people/81965/?format=json","name":"Akhil R","email":"akhilrajeev@nvidia.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-tegra/patch/20260505105928.38457-3-akhilrajeev@nvidia.com/mbox/","series":[{"id":502821,"url":"http://patchwork.ozlabs.org/api/1.2/series/502821/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-tegra/list/?series=502821","date":"2026-05-05T10:59:25","name":"i2c: tegra: Improve DMA mapping, latency, and power management","version":1,"mbox":"http://patchwork.ozlabs.org/series/502821/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2232958/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2232958/checks/","tags":{},"related":[],"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-tegra@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=sZZHn+Xy;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.105.105.114; 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It is enabled by default, adding a per-transfer latency overhead\nthat impacts non-MCTP I2C buses.\n\nDisable the fairness arbitration register during controller init for buses\nthat are not MCTP controllers.\n\nSigned-off-by: Akhil R \nAssisted-by: Cursor:claude-4.6-opus\n---\n drivers/i2c/busses/i2c-tegra.c | 23 +++++++++++++++++++++++\n 1 file changed, 23 insertions(+)","diff":"diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c\nindex a21f6457d41b..1d274431e209 100644\n--- a/drivers/i2c/busses/i2c-tegra.c\n+++ b/drivers/i2c/busses/i2c-tegra.c\n@@ -164,6 +164,7 @@ struct tegra_i2c_regs {\n \tunsigned int master_reset_cntrl;\n \tunsigned int mst_fifo_control;\n \tunsigned int mst_fifo_status;\n+\tunsigned int fairness_arb;\n \tunsigned int sw_mutex;\n };\n \n@@ -272,6 +273,7 @@ static const struct tegra_i2c_regs tegra264_i2c_regs = {\n \t.master_reset_cntrl = 0x0a8,\n \t.mst_fifo_control = 0x0b4,\n \t.mst_fifo_status = 0x0b8,\n+\t.fairness_arb = 0x0e8,\n \t.sw_mutex = 0x0ec,\n };\n \n@@ -300,6 +302,7 @@ static const struct tegra_i2c_regs tegra410_i2c_regs = {\n \t.master_reset_cntrl = 0x0ac,\n \t.mst_fifo_control = 0x0b8,\n \t.mst_fifo_status = 0x0bc,\n+\t.fairness_arb = 0x0ec,\n \t.sw_mutex = 0x0f0,\n };\n \n@@ -379,6 +382,7 @@ enum tegra_i2c_variant {\n *\t\ttiming settings.\n * @enable_hs_mode_support: Enable support for high speed (HS) mode transfers.\n * @has_mutex: Has mutex register for mutual exclusion with other firmwares or VMs.\n+ * @has_fairarb_reg: Has fairness arbitration register for SMBUS/MCTP support.\n * @variant: This represents the I2C controller variant.\n * @regs: Register offsets for the specific SoC variant.\n */\n@@ -412,6 +416,7 @@ struct tegra_i2c_hw_feature {\n \tbool has_interface_timing_reg;\n \tbool enable_hs_mode_support;\n \tbool has_mutex;\n+\tbool has_fairarb_reg;\n \tenum tegra_i2c_variant variant;\n \tconst struct tegra_i2c_regs *regs;\n };\n@@ -476,6 +481,7 @@ struct tegra_i2c_dev {\n \tvoid *dma_buf;\n \n \tbool multimaster_mode;\n+\tbool is_mctp;\n \tbool atomic_mode;\n \tbool dma_mode;\n \tbool msg_read;\n@@ -914,6 +920,10 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)\n \tif (IS_VI(i2c_dev))\n \t\ttegra_i2c_vi_init(i2c_dev);\n \n+\t/* Disable fairness arbitration if not an MCTP controller */\n+\tif (i2c_dev->hw->has_fairarb_reg && !i2c_dev->is_mctp)\n+\t\ti2c_writel(i2c_dev, 0, i2c_dev->hw->regs->fairness_arb);\n+\n \tif (i2c_dev->hw->enable_hs_mode_support)\n \t\tmax_bus_freq_hz = I2C_MAX_HIGH_SPEED_MODE_FREQ;\n \telse\n@@ -1779,6 +1789,7 @@ static const struct tegra_i2c_hw_feature tegra20_i2c_hw = {\n \t.has_interface_timing_reg = false,\n \t.enable_hs_mode_support = false,\n \t.has_mutex = false,\n+\t.has_fairarb_reg = false,\n \t.variant = TEGRA_I2C_VARIANT_DEFAULT,\n \t.regs = &tegra20_i2c_regs,\n };\n@@ -1812,6 +1823,7 @@ static const struct tegra_i2c_hw_feature tegra20_dvc_i2c_hw = {\n \t.has_interface_timing_reg = false,\n \t.enable_hs_mode_support = false,\n \t.has_mutex = false,\n+\t.has_fairarb_reg = false,\n \t.variant = TEGRA_I2C_VARIANT_DVC,\n \t.regs = &tegra20_dvc_i2c_regs,\n };\n@@ -1845,6 +1857,7 @@ static const struct tegra_i2c_hw_feature tegra30_i2c_hw = {\n \t.has_interface_timing_reg = false,\n \t.enable_hs_mode_support = false,\n \t.has_mutex = false,\n+\t.has_fairarb_reg = false,\n \t.variant = TEGRA_I2C_VARIANT_DEFAULT,\n \t.regs = &tegra20_i2c_regs,\n };\n@@ -1877,6 +1890,7 @@ static const struct tegra_i2c_hw_feature tegra114_i2c_hw = {\n \t.has_interface_timing_reg = false,\n \t.enable_hs_mode_support = false,\n \t.has_mutex = false,\n+\t.has_fairarb_reg = false,\n \t.variant = TEGRA_I2C_VARIANT_DEFAULT,\n \t.regs = &tegra20_i2c_regs,\n };\n@@ -1909,6 +1923,7 @@ static const struct tegra_i2c_hw_feature tegra124_i2c_hw = {\n \t.has_interface_timing_reg = true,\n \t.enable_hs_mode_support = false,\n \t.has_mutex = false,\n+\t.has_fairarb_reg = false,\n \t.variant = TEGRA_I2C_VARIANT_DEFAULT,\n \t.regs = &tegra20_i2c_regs,\n };\n@@ -1941,6 +1956,7 @@ static const struct tegra_i2c_hw_feature tegra210_i2c_hw = {\n \t.has_interface_timing_reg = true,\n \t.enable_hs_mode_support = false,\n \t.has_mutex = false,\n+\t.has_fairarb_reg = false,\n \t.variant = TEGRA_I2C_VARIANT_DEFAULT,\n \t.regs = &tegra20_i2c_regs,\n };\n@@ -1974,6 +1990,7 @@ static const struct tegra_i2c_hw_feature tegra210_vi_i2c_hw = {\n \t.has_interface_timing_reg = true,\n \t.enable_hs_mode_support = false,\n \t.has_mutex = false,\n+\t.has_fairarb_reg = false,\n \t.variant = TEGRA_I2C_VARIANT_VI,\n \t.regs = &tegra210_vi_i2c_regs,\n };\n@@ -2007,6 +2024,7 @@ static const struct tegra_i2c_hw_feature tegra186_i2c_hw = {\n \t.has_interface_timing_reg = true,\n \t.enable_hs_mode_support = false,\n \t.has_mutex = false,\n+\t.has_fairarb_reg = false,\n \t.variant = TEGRA_I2C_VARIANT_DEFAULT,\n \t.regs = &tegra20_i2c_regs,\n };\n@@ -2041,6 +2059,7 @@ static const struct tegra_i2c_hw_feature tegra194_i2c_hw = {\n \t.has_interface_timing_reg = true,\n \t.enable_hs_mode_support = true,\n \t.has_mutex = false,\n+\t.has_fairarb_reg = false,\n \t.variant = TEGRA_I2C_VARIANT_DEFAULT,\n \t.regs = &tegra20_i2c_regs,\n };\n@@ -2075,6 +2094,7 @@ static const struct tegra_i2c_hw_feature tegra256_i2c_hw = {\n \t.has_interface_timing_reg = true,\n \t.enable_hs_mode_support = true,\n \t.has_mutex = true,\n+\t.has_fairarb_reg = true,\n \t.variant = TEGRA_I2C_VARIANT_DEFAULT,\n \t.regs = &tegra264_i2c_regs,\n };\n@@ -2109,6 +2129,7 @@ static const struct tegra_i2c_hw_feature tegra264_i2c_hw = {\n \t.has_interface_timing_reg = true,\n \t.enable_hs_mode_support = true,\n \t.has_mutex = true,\n+\t.has_fairarb_reg = true,\n \t.variant = TEGRA_I2C_VARIANT_DEFAULT,\n \t.regs = &tegra264_i2c_regs,\n };\n@@ -2143,6 +2164,7 @@ static const struct tegra_i2c_hw_feature tegra410_i2c_hw = {\n \t.has_interface_timing_reg = true,\n \t.enable_hs_mode_support = true,\n \t.has_mutex = true,\n+\t.has_fairarb_reg = true,\n \t.variant = TEGRA_I2C_VARIANT_DEFAULT,\n \t.regs = &tegra410_i2c_regs,\n };\n@@ -2175,6 +2197,7 @@ static void tegra_i2c_parse_dt(struct tegra_i2c_dev *i2c_dev)\n \n \tmulti_mode = device_property_read_bool(i2c_dev->dev, \"multi-master\");\n \ti2c_dev->multimaster_mode = multi_mode;\n+\ti2c_dev->is_mctp = device_property_present(i2c_dev->dev, \"mctp-controller\");\n }\n \n static int tegra_i2c_init_clocks(struct tegra_i2c_dev *i2c_dev)\n","prefixes":["2/4"]}