{"id":2232947,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2232947/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-i2c/patch/20260505105928.38457-2-akhilrajeev@nvidia.com/","project":{"id":35,"url":"http://patchwork.ozlabs.org/api/1.2/projects/35/?format=json","name":"Linux I2C development","link_name":"linux-i2c","list_id":"linux-i2c.vger.kernel.org","list_email":"linux-i2c@vger.kernel.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260505105928.38457-2-akhilrajeev@nvidia.com>","list_archive_url":null,"date":"2026-05-05T10:59:25","name":"[1/4] i2c: tegra: use dmaengine_get_dma_device() for DMA buffer allocation","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"9ee681c1d6fe41f61ffb490157d22e8876423501","submitter":{"id":81965,"url":"http://patchwork.ozlabs.org/api/1.2/people/81965/?format=json","name":"Akhil R","email":"akhilrajeev@nvidia.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-i2c/patch/20260505105928.38457-2-akhilrajeev@nvidia.com/mbox/","series":[{"id":502818,"url":"http://patchwork.ozlabs.org/api/1.2/series/502818/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-i2c/list/?series=502818","date":"2026-05-05T10:59:25","name":"i2c: tegra: Improve DMA mapping, latency, and power management","version":1,"mbox":"http://patchwork.ozlabs.org/series/502818/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2232947/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2232947/checks/","tags":{},"related":[],"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-i2c@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=WOvyus6+;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.105.105.114; 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dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=nvidia.com;","Received-SPF":"Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.117.160 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C","From":"Akhil R ","To":"Laxman Dewangan , Dmitry Osipenko\n\t, Andi Shyti , Thierry Reding\n\t, Jonathan Hunter , \"Kartik\n Rajput\" , Wolfram Sang ,\n\t, ,\n\t","CC":", Akhil R ","Subject":"[PATCH 1/4] i2c: tegra: use dmaengine_get_dma_device() for DMA buffer\n allocation","Date":"Tue, 5 May 2026 16:29:25 +0530","Message-ID":"<20260505105928.38457-2-akhilrajeev@nvidia.com>","X-Mailer":"git-send-email 2.50.1","In-Reply-To":"<20260505105928.38457-1-akhilrajeev@nvidia.com>","References":"<20260505105928.38457-1-akhilrajeev@nvidia.com>","Precedence":"bulk","X-Mailing-List":"linux-i2c@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","X-NVConfidentiality":"public","Content-Transfer-Encoding":"8bit","Content-Type":"text/plain","X-NV-OnPremToCloud":"ExternallySecured","X-EOPAttributedMessage":"0","X-MS-PublicTrafficType":"Email","X-MS-TrafficTypeDiagnostic":"BL02EPF00021F6C:EE_|CH1PR12MB9599:EE_","X-MS-Office365-Filtering-Correlation-Id":"d65fc1e0-e36a-452a-4e3e-08deaa9575fb","X-MS-Exchange-SenderADCheck":"1","X-MS-Exchange-AntiSpam-Relay":"0","X-Microsoft-Antispam":"\n\tBCL:0;ARA:13230040|82310400026|36860700016|1800799024|376014|921020|56012099003|22082099003|18002099003;","X-Microsoft-Antispam-Message-Info":"\n\tZTU/JK+wFwNgYEK+CN417z7iMZJLOFItDpmlE6UrRnRrFNwGCRXh67UCB/cAw/wATSPIbB61kCJ2RGfChamoLhr0ME4QzrPrK9ovYY2mBvUjrsD1SvGxlapXheNFCjWNkMPEcm/KQe7g9TyNvI7yjkxEDvA6NvSM4qVvlK4VftbcOqsFCoBWQpDSjjOWCY8QY7gr80jOyFtyeyI8n+HHkjW9PqwgibxYsxjKxM8En1gO1ROhoIMEpivCfMfpehLCfAgKUIRkPPIl4p5Zk+34i/GwsSeuQKgUwu07i/DpufymAMmMGPgJxG4peM/jvU8bTVrjQa6/IkFP/cSIKVcl7k8gAC+DxyDKOqg4NeaZ41mrXPgRNre0ax7PEyX9dt2FucUTQ8hEQJwLfZ9jydFScU4l4uj6eQh6xUWggHI4sUV3YTD1idgLN7sN3K3IjktXT0LK3EEh7rOaQesIBgh3lwE6ay+Eqy4N98Q22K73T9WM/LOUeqbRUJ+qQS7kZw5eSwLmt9ENeQ8M3xP9yVKs5yMDCS0yyRDmZVQsQmkWcxCScJyhqQPhHjQelgpHugxa+Fnyx8AVI6knUTzjxX9JP1pIEogmBaXBgo1iiV9DdXUDphPtojiSgusbLSUProowKHp6fN501tqxoXBu6deO8G2LtWc3lAXDyhMdXaTbL38Ga5y1m056DxOQxdyIgeW6BUeCJyN1Lp8RgvBKPbpjprhMhGg6Xg9JwBHyf7L9Ks6gW1zZ629+6bzTDl0pnToVxNb7tL9WCIMGcQdSCaS14g==","X-Forefront-Antispam-Report":"\n\tCIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(36860700016)(1800799024)(376014)(921020)(56012099003)(22082099003)(18002099003);DIR:OUT;SFP:1101;","X-MS-Exchange-AntiSpam-MessageData-ChunkCount":"1","X-MS-Exchange-AntiSpam-MessageData-0":"\n\tjuVmsdPOlRCaYQ1o2JL7ANkmkjKWhCk3/45R2FVkc1wTJRmaqXOcDLUqxBfent6iWLC7UaaYf9Cgv+R1nwV9Pzq32X4myw4LjfZs8/Cg+Jxb9BmPiVQvIzpyFezhfyZcXb6yNKwDfqfjcGBHGRPa4Ens1cGBsUz3Q2qWyDgasL3ReuBR4AzhQs/V9lWWmpPT/pN3k/xM8awT5ykA5m+OYjdkUrLT66X8qfAR0MHTbK3V6kQmm4Cz+amxloyxG+h9rPI0M6aCQWFi1DSSF6SWSuasryKGwVACz1rAVkGMsKGUX8XBQgaAllLPIQzdijQmg5xQ2dlM2984NF5irfUyI9Du5aREDij8POX44Dphe4rcB8aHj9U4wvyA1bewPG866pZJf6ayGeeUtIX/OGfkeUv+LN/5sHyaYmEeU9ui9LXNISPh68IdrBSQJktA29qX","X-OriginatorOrg":"Nvidia.com","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"05 May 2026 11:00:03.7572\n (UTC)","X-MS-Exchange-CrossTenant-Network-Message-Id":"\n d65fc1e0-e36a-452a-4e3e-08deaa9575fb","X-MS-Exchange-CrossTenant-Id":"43083d15-7273-40c1-b7db-39efd9ccc17a","X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp":"\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com]","X-MS-Exchange-CrossTenant-AuthSource":"\n\tBL02EPF00021F6C.namprd02.prod.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Anonymous","X-MS-Exchange-CrossTenant-FromEntityHeader":"HybridOnPrem","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"CH1PR12MB9599"},"content":"Use dmaengine_get_dma_device() to obtain the correct struct device\npointer for dma_alloc_coherent() instead of directly dereferencing\nchan->device->dev.\n\nThe dmaengine_get_dma_device() helper checks whether the DMA channel\nhas a per-channel DMA device (chan->dev->chan_dma_dev) and returns it\nwhen available, falling back to the controller device otherwise. On\nplatforms where the DMA controller sits behind an IOMMU with\nper-channel IOVA spaces (e.g. Tegra264 GPC DMA), the per-channel\ndevice carries the correct DMA mapping context. Using the controller\ndevice directly would allocate DMA buffers against the wrong IOMMU\ndomain, leading to SMMU faults at runtime.\n\nOn platforms without per-channel DMA devices the helper returns the\nsame pointer as before, so there is no change in behavior for existing\nhardware.\n\nSigned-off-by: Akhil R \nAssisted-by: Cursor:claude-4.6-opus\n---\n drivers/i2c/busses/i2c-tegra.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)","diff":"diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c\nindex 9fd5ade774a0..a21f6457d41b 100644\n--- a/drivers/i2c/busses/i2c-tegra.c\n+++ b/drivers/i2c/busses/i2c-tegra.c\n@@ -712,7 +712,7 @@ static int tegra_i2c_init_dma(struct tegra_i2c_dev *i2c_dev)\n \t\tgoto err_out;\n \t}\n \n-\ti2c_dev->dma_dev = i2c_dev->dma_chan->device->dev;\n+\ti2c_dev->dma_dev = dmaengine_get_dma_device(i2c_dev->dma_chan);\n \ti2c_dev->dma_buf_size = i2c_dev->hw->quirks->max_write_len +\n \t\t\t\tI2C_PACKET_HEADER_SIZE;\n \n","prefixes":["1/4"]}