{"id":2232168,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2232168/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260503073541.790215-11-eric.auger@redhat.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260503073541.790215-11-eric.auger@redhat.com>","list_archive_url":null,"date":"2026-05-03T07:33:30","name":"[v4,10/17] arm/kvm: Allow reading all the writable ID registers","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"f547e69ba5df9247b7c85dbc4f27ace779d57e57","submitter":{"id":69187,"url":"http://patchwork.ozlabs.org/api/1.2/people/69187/?format=json","name":"Eric Auger","email":"eric.auger@redhat.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260503073541.790215-11-eric.auger@redhat.com/mbox/","series":[{"id":502569,"url":"http://patchwork.ozlabs.org/api/1.2/series/502569/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502569","date":"2026-05-03T07:33:20","name":"kvm/arm: Introduce a customizable aarch64 KVM host model","version":4,"mbox":"http://patchwork.ozlabs.org/series/502569/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2232168/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2232168/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=redhat.com header.i=@redhat.com header.a=rsa-sha256\n header.s=mimecast20190719 header.b=SUwmH8KB;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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a=rsa-sha256; c=relaxed/relaxed; d=redhat.com;\n s=mimecast20190719; t=1777793816;\n h=from:from:reply-to:subject:subject:date:date:message-id:message-id:\n to:to:cc:cc:mime-version:mime-version:\n content-transfer-encoding:content-transfer-encoding:\n in-reply-to:in-reply-to:references:references;\n bh=Ww7xxuY6m4aLvO5gFffSVqL+WmEUwMUCi1aQsJoWLbo=;\n b=SUwmH8KBp2gaTp4/L2/sNwoXa69LAsZXWF364onaMxUiGbSdLlKKz4mskXzwxqmZPbxfnN\n RUPzBcZz19yY/OqjGuXHxKYj14VhMPOv8ZNpC1qO+GYJZ+NcjomAhj5hmaaPLhtLHA0SJ4\n 3JoYFPlfsIY6tpb8QpDlvtv/6yoFYCA=","X-MC-Unique":"ZoeRi9uCMOyfKA2bc3VMCA-1","X-Mimecast-MFC-AGG-ID":"ZoeRi9uCMOyfKA2bc3VMCA_1777793810","From":"Eric Auger ","To":"eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org,\n qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org,\n richard.henderson@linaro.org, cohuck@redhat.com, sebott@redhat.com,\n skolothumtho@nvidia.com, philmd@linaro.org","Cc":"maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com,\n armbru@redhat.com, berrange@redhat.com, abologna@redhat.com,\n jdenemar@redhat.com","Subject":"[PATCH v4 10/17] arm/kvm: Allow reading all the writable ID registers","Date":"Sun, 3 May 2026 09:33:30 +0200","Message-ID":"<20260503073541.790215-11-eric.auger@redhat.com>","In-Reply-To":"<20260503073541.790215-1-eric.auger@redhat.com>","References":"<20260503073541.790215-1-eric.auger@redhat.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-Scanned-By":"MIMEDefang 3.4.1 on 10.30.177.93","Received-SPF":"pass client-ip=170.10.133.124;\n envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com","X-Spam_score_int":"12","X-Spam_score":"1.2","X-Spam_bar":"+","X-Spam_report":"(1.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001,\n RCVD_IN_SBL_CSS=3.335, SPF_HELO_PASS=-0.001,\n SPF_PASS=-0.001 autolearn=no autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"At the moment kvm_arm_get_host_cpu_features() reads a subset of the\nID regs. As we want to introduce properties for all writable ID reg\nfields, we want more genericity and read more default host register\nvalues.\n\nIntroduce a new get_host_cpu_idregs() helper and add a new exhaustive\nboolean parameter to kvm_arm_get_host_cpu_features() and\nkvm_arm_set_cpu_features_from_host() to select the right behavior.\nThe host cpu model will keep the legacy behavior unless the writable\nid register interface is available.\n\nA writable_map IdRegMap is introduced in the CPU object. A subsequent\npatch will populate it.\n\nSigned-off-by: Eric Auger \nSigned-off-by: Cornelia Huck \n---\n target/arm/cpu.h | 3 ++\n target/arm/cpu64.c | 2 +-\n target/arm/kvm-stub.c | 3 +-\n target/arm/kvm.c | 77 +++++++++++++++++++++++++++++++++++++++--\n target/arm/kvm_arm.h | 6 +++-\n target/arm/trace-events | 1 +\n 6 files changed, 86 insertions(+), 6 deletions(-)","diff":"diff --git a/target/arm/cpu.h b/target/arm/cpu.h\nindex 0ac0fd13cf..87fb0047eb 100644\n--- a/target/arm/cpu.h\n+++ b/target/arm/cpu.h\n@@ -1087,6 +1087,9 @@ struct ArchCPU {\n */\n ARMIdRegsState writable_id_regs_status;\n \n+ /* ID reg writable bitmask (KVM only) */\n+ IdRegMap *writable_map;\n+\n /* QOM property to indicate we should use the back-compat CNTFRQ default */\n bool backcompat_cntfrq;\n \ndiff --git a/target/arm/cpu64.c b/target/arm/cpu64.c\nindex b940842d9e..1b3d3fb245 100644\n--- a/target/arm/cpu64.c\n+++ b/target/arm/cpu64.c\n@@ -862,7 +862,7 @@ static void aarch64_host_initfn(Object *obj)\n \n #if defined(CONFIG_KVM)\n kvm_arm_set_cpreg_mig_tolerances(cpu);\n- kvm_arm_set_cpu_features_from_host(cpu);\n+ kvm_arm_set_cpu_features_from_host(cpu, false);\n aarch64_add_sve_properties(obj);\n #elif defined(CONFIG_HVF)\n hvf_arm_set_cpu_features_from_host(cpu);\ndiff --git a/target/arm/kvm-stub.c b/target/arm/kvm-stub.c\nindex 88cbe8d85c..94478c5690 100644\n--- a/target/arm/kvm-stub.c\n+++ b/target/arm/kvm-stub.c\n@@ -45,7 +45,8 @@ bool kvm_arm_el2_supported(void)\n /*\n * These functions should never actually be called without KVM support.\n */\n-void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu)\n+void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu,\n+ bool get_all_writable_id_regs)\n {\n g_assert_not_reached();\n }\ndiff --git a/target/arm/kvm.c b/target/arm/kvm.c\nindex f06a60804d..1a9b91bf8a 100644\n--- a/target/arm/kvm.c\n+++ b/target/arm/kvm.c\n@@ -42,6 +42,7 @@\n #include \"hw/acpi/ghes.h\"\n #include \"target/arm/gtimer.h\"\n #include \"migration/blocker.h\"\n+#include \"cpu-idregs.h\"\n \n const KVMCapabilityInfo kvm_arch_required_capabilities[] = {\n KVM_CAP_INFO(DEVICE_CTRL),\n@@ -274,7 +275,63 @@ static uint32_t kvm_arm_sve_get_vls(int fd)\n return vls[0] & MAKE_64BIT_MASK(0, ARM_MAX_VQ);\n }\n \n-static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)\n+static int idregs_idx_to_kvm_feature_idx(ARMIDRegisterIdx idx)\n+{\n+ ARMSysRegs sysreg = id_register_sysreg[idx];\n+\n+ return KVM_ARM_FEATURE_ID_RANGE_IDX((sysreg & CP_REG_ARM64_SYSREG_OP0_MASK)\n+ >> CP_REG_ARM64_SYSREG_OP0_SHIFT,\n+ (sysreg & CP_REG_ARM64_SYSREG_OP1_MASK)\n+ >> CP_REG_ARM64_SYSREG_OP1_SHIFT,\n+ (sysreg & CP_REG_ARM64_SYSREG_CRN_MASK)\n+ >> CP_REG_ARM64_SYSREG_CRN_SHIFT,\n+ (sysreg & CP_REG_ARM64_SYSREG_CRM_MASK)\n+ >> CP_REG_ARM64_SYSREG_CRM_SHIFT,\n+ (sysreg & CP_REG_ARM64_SYSREG_OP2_MASK)\n+ >> CP_REG_ARM64_SYSREG_OP2_SHIFT);\n+}\n+\n+/*\n+ * get_host_cpu_idregs: Read all the writable ID reg host values\n+ *\n+ * Need to be called once the writable mask has been populated\n+ * Note we may want to read all the known id regs but some of them are not\n+ * writable and return an error, hence the choice of reading only those which\n+ * are writable. Those are also readable!\n+ */\n+static int get_host_cpu_idregs(ARMCPU *cpu, int fd, ARMHostCPUFeatures *ahcf)\n+{\n+ int err = 0;\n+ int i;\n+\n+ for (i = 0; i < NUM_ID_IDX; i++) {\n+ ARM64SysReg *sysregdesc = &arm64_id_regs[i];\n+ ARMSysRegs sysreg = sysregdesc->sysreg;\n+ uint64_t writable_mask =\n+ cpu->writable_map->regs[idregs_idx_to_kvm_feature_idx(i)];\n+ uint64_t *reg;\n+ int ret;\n+\n+ if (!writable_mask) {\n+ continue;\n+ }\n+\n+ reg = &ahcf->isar.idregs[i];\n+ ret = read_sys_reg64(fd, reg, idregs_sysreg_to_kvm_reg(sysreg));\n+ trace_get_host_cpu_idregs(sysregdesc->name, *reg);\n+ if (ret) {\n+ error_report(\"%s error reading value of host %s register (%m)\",\n+ __func__, sysregdesc->name);\n+\n+ err = ret;\n+ }\n+ }\n+ return err;\n+}\n+\n+static bool\n+kvm_arm_get_host_cpu_features(ARMCPU *cpu, ARMHostCPUFeatures *ahcf,\n+ bool get_all_writable_id_regs)\n {\n /* Identify the feature bits corresponding to the host CPU, and\n * fill out the ARMHostCPUClass fields accordingly. To do this\n@@ -401,6 +458,18 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)\n err |= get_host_cpu_reg(fd, ahcf, ID_DFR1_EL1_IDX);\n err |= get_host_cpu_reg(fd, ahcf, ID_MMFR5_EL1_IDX);\n \n+ /* Make sure writable ID reg values are read */\n+ if (get_all_writable_id_regs) {\n+ err |= get_host_cpu_idregs(cpu, fd, ahcf);\n+ }\n+\n+ /*\n+ * temporarily override the CLIDR_EL1 value since host value does\n+ * not seem to be supported. Getting \"Unified type is not implemented\n+ * at level n\" error in fdt_add_cpu_nodes()\n+ */\n+ SET_IDREG(&ahcf->isar, CLIDR, 0x0);\n+\n /*\n * DBGDIDR is a bit complicated because the kernel doesn't\n * provide an accessor for it in 64-bit mode, which is what this\n@@ -477,13 +546,15 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)\n return true;\n }\n \n-void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu)\n+void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu,\n+ bool get_all_writable_id_regs)\n {\n CPUARMState *env = &cpu->env;\n \n if (!arm_host_cpu_features.dtb_compatible) {\n if (!kvm_enabled() ||\n- !kvm_arm_get_host_cpu_features(&arm_host_cpu_features)) {\n+ !kvm_arm_get_host_cpu_features(cpu, &arm_host_cpu_features,\n+ get_all_writable_id_regs)) {\n /* We can't report this error yet, so flag that we need to\n * in arm_cpu_realizefn().\n */\ndiff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h\nindex b22a56fc17..91a7d5cc4b 100644\n--- a/target/arm/kvm_arm.h\n+++ b/target/arm/kvm_arm.h\n@@ -127,11 +127,15 @@ void kvm_arm_destroy_scratch_host_vcpu(int *fdarray);\n /**\n * kvm_arm_set_cpu_features_from_host:\n * @cpu: ARMCPU to set the features for\n+ * @get_all_writable_id_regs: if true, get the contents of all writable ID\n+ * registers as well\n *\n * Set up the ARMCPU struct fields up to match the information probed\n * from the host CPU.\n+ *\n */\n-void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu);\n+void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu,\n+ bool get_all_writable_id_regs);\n \n /**\n * kvm_arm_add_vcpu_properties:\ndiff --git a/target/arm/trace-events b/target/arm/trace-events\nindex 8502fb3265..8c7faf57c7 100644\n--- a/target/arm/trace-events\n+++ b/target/arm/trace-events\n@@ -13,6 +13,7 @@ arm_gt_update_irq(int timer, int irqstate) \"gt_update_irq: timer %d irqstate %d\"\n \n # kvm.c\n kvm_arm_fixup_msi_route(uint64_t iova, uint64_t gpa) \"MSI iova = 0x%\"PRIx64\" is translated into 0x%\"PRIx64\n+get_host_cpu_idregs(const char *name, uint64_t value) \"scratch vcpu host value for %s is 0x%\"PRIx64\n \n # cpu.c\n arm_cpu_reset(uint64_t mp_aff) \"cpu %\" PRIu64\n","prefixes":["v4","10/17"]}