{"id":2232153,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2232153/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260503073541.790215-3-eric.auger@redhat.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260503073541.790215-3-eric.auger@redhat.com>","list_archive_url":null,"date":"2026-05-03T07:33:22","name":"[v4,02/17] target/arm/cpu-sysregs.h.inc: Sort by name alphabetical order","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"9d7fe8562f8662f8483651fcc573b44978b057fe","submitter":{"id":69187,"url":"http://patchwork.ozlabs.org/api/1.2/people/69187/?format=json","name":"Eric Auger","email":"eric.auger@redhat.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260503073541.790215-3-eric.auger@redhat.com/mbox/","series":[{"id":502569,"url":"http://patchwork.ozlabs.org/api/1.2/series/502569/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502569","date":"2026-05-03T07:33:20","name":"kvm/arm: Introduce a customizable aarch64 KVM host model","version":4,"mbox":"http://patchwork.ozlabs.org/series/502569/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2232153/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2232153/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=redhat.com header.i=@redhat.com header.a=rsa-sha256\n header.s=mimecast20190719 header.b=Fml+tSEo;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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a=rsa-sha256; c=relaxed/relaxed; d=redhat.com;\n s=mimecast20190719; t=1777793770;\n h=from:from:reply-to:subject:subject:date:date:message-id:message-id:\n to:to:cc:cc:mime-version:mime-version:\n content-transfer-encoding:content-transfer-encoding:\n in-reply-to:in-reply-to:references:references;\n bh=ol6jjCc0cvYMVJdnI2W+QVeN430AK+kQr2vrJR0Z0lQ=;\n b=Fml+tSEosq96/STPvS/WDkiWTyhiSp19AgWaNRaOcw/lauSDgFeKC8GrxUaol1k35nZTSH\n m6BKcfpKcFyDGy1WYrdMmDNp1Dcej84V9omCVBBGPHDd24f4TeZoy0aCKrobWvCkX+KB5x\n UdZOUYdEnepzfg/afzhBqMWMqVW9n/I=","X-MC-Unique":"beDU38yWMFCltsFOYgz8Og-1","X-Mimecast-MFC-AGG-ID":"beDU38yWMFCltsFOYgz8Og_1777793765","From":"Eric Auger ","To":"eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org,\n qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org,\n richard.henderson@linaro.org, cohuck@redhat.com, sebott@redhat.com,\n skolothumtho@nvidia.com, philmd@linaro.org","Cc":"maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com,\n armbru@redhat.com, berrange@redhat.com, abologna@redhat.com,\n jdenemar@redhat.com","Subject":"[PATCH v4 02/17] target/arm/cpu-sysregs.h.inc: Sort by name\n alphabetical order","Date":"Sun, 3 May 2026 09:33:22 +0200","Message-ID":"<20260503073541.790215-3-eric.auger@redhat.com>","In-Reply-To":"<20260503073541.790215-1-eric.auger@redhat.com>","References":"<20260503073541.790215-1-eric.auger@redhat.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-Scanned-By":"MIMEDefang 3.4.1 on 10.30.177.93","Received-SPF":"pass client-ip=170.10.129.124;\n envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001,\n SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"target/arm/cpu-sysregs.h.inc: Sort by name alphabetical order\n\nSort by register name alphabetical order. This will allow to\neasily diff with the future content, automatically generated.\n\nNo functional change intended.\n\nSigned-off-by: Eric Auger \nSigned-off-by: Cornelia Huck \nMessage-ID: <20251208163751.611186-3-eric.auger@redhat.com>\n---\n target/arm/cpu-sysregs.h.inc | 43 ++++++++++++++++++------------------\n 1 file changed, 22 insertions(+), 21 deletions(-)","diff":"diff --git a/target/arm/cpu-sysregs.h.inc b/target/arm/cpu-sysregs.h.inc\nindex 3d1ed40f04..d61f0d0a19 100644\n--- a/target/arm/cpu-sysregs.h.inc\n+++ b/target/arm/cpu-sysregs.h.inc\n@@ -1,12 +1,12 @@\n /* SPDX-License-Identifier: GPL-2.0-or-later */\n-DEF(ID_AA64PFR0_EL1, 3, 0, 0, 4, 0)\n-DEF(ID_AA64PFR1_EL1, 3, 0, 0, 4, 1)\n-DEF(ID_AA64PFR2_EL1, 3, 0, 0, 4, 2)\n-DEF(ID_AA64SMFR0_EL1, 3, 0, 0, 4, 5)\n-DEF(ID_AA64DFR0_EL1, 3, 0, 0, 5, 0)\n-DEF(ID_AA64DFR1_EL1, 3, 0, 0, 5, 1)\n+DEF(CCSIDR_EL1, 3, 1, 0, 0, 0)\n+DEF(CLIDR_EL1, 3, 1, 0, 0, 1)\n+DEF(CTR_EL0, 3, 3, 0, 0, 1)\n+DEF(DCZID_EL0, 3, 3, 0, 0, 7)\n DEF(ID_AA64AFR0_EL1, 3, 0, 0, 5, 4)\n DEF(ID_AA64AFR1_EL1, 3, 0, 0, 5, 5)\n+DEF(ID_AA64DFR0_EL1, 3, 0, 0, 5, 0)\n+DEF(ID_AA64DFR1_EL1, 3, 0, 0, 5, 1)\n DEF(ID_AA64ISAR0_EL1, 3, 0, 0, 6, 0)\n DEF(ID_AA64ISAR1_EL1, 3, 0, 0, 6, 1)\n DEF(ID_AA64ISAR2_EL1, 3, 0, 0, 6, 2)\n@@ -15,29 +15,30 @@ DEF(ID_AA64MMFR1_EL1, 3, 0, 0, 7, 1)\n DEF(ID_AA64MMFR2_EL1, 3, 0, 0, 7, 2)\n DEF(ID_AA64MMFR3_EL1, 3, 0, 0, 7, 3)\n DEF(ID_AA64MMFR4_EL1, 3, 0, 0, 7, 4)\n-DEF(ID_PFR0_EL1, 3, 0, 0, 1, 0)\n-DEF(ID_PFR1_EL1, 3, 0, 0, 1, 1)\n-DEF(ID_DFR0_EL1, 3, 0, 0, 1, 2)\n+DEF(ID_AA64PFR0_EL1, 3, 0, 0, 4, 0)\n+DEF(ID_AA64PFR1_EL1, 3, 0, 0, 4, 1)\n+DEF(ID_AA64PFR2_EL1, 3, 0, 0, 4, 2)\n+DEF(ID_AA64SMFR0_EL1, 3, 0, 0, 4, 5)\n+DEF(ID_AA64ZFR0_EL1, 3, 0, 0, 4, 4)\n DEF(ID_AFR0_EL1, 3, 0, 0, 1, 3)\n-DEF(ID_MMFR0_EL1, 3, 0, 0, 1, 4)\n-DEF(ID_MMFR1_EL1, 3, 0, 0, 1, 5)\n-DEF(ID_MMFR2_EL1, 3, 0, 0, 1, 6)\n-DEF(ID_MMFR3_EL1, 3, 0, 0, 1, 7)\n+DEF(ID_DFR0_EL1, 3, 0, 0, 1, 2)\n+DEF(ID_DFR1_EL1, 3, 0, 0, 3, 5)\n DEF(ID_ISAR0_EL1, 3, 0, 0, 2, 0)\n DEF(ID_ISAR1_EL1, 3, 0, 0, 2, 1)\n DEF(ID_ISAR2_EL1, 3, 0, 0, 2, 2)\n DEF(ID_ISAR3_EL1, 3, 0, 0, 2, 3)\n DEF(ID_ISAR4_EL1, 3, 0, 0, 2, 4)\n DEF(ID_ISAR5_EL1, 3, 0, 0, 2, 5)\n-DEF(ID_MMFR4_EL1, 3, 0, 0, 2, 6)\n DEF(ID_ISAR6_EL1, 3, 0, 0, 2, 7)\n+DEF(ID_MMFR0_EL1, 3, 0, 0, 1, 4)\n+DEF(ID_MMFR1_EL1, 3, 0, 0, 1, 5)\n+DEF(ID_MMFR2_EL1, 3, 0, 0, 1, 6)\n+DEF(ID_MMFR3_EL1, 3, 0, 0, 1, 7)\n+DEF(ID_MMFR4_EL1, 3, 0, 0, 2, 6)\n+DEF(ID_MMFR5_EL1, 3, 0, 0, 3, 6)\n+DEF(ID_PFR0_EL1, 3, 0, 0, 1, 0)\n+DEF(ID_PFR1_EL1, 3, 0, 0, 1, 1)\n+DEF(ID_PFR2_EL1, 3, 0, 0, 3, 4)\n DEF(MVFR0_EL1, 3, 0, 0, 3, 0)\n DEF(MVFR1_EL1, 3, 0, 0, 3, 1)\n DEF(MVFR2_EL1, 3, 0, 0, 3, 2)\n-DEF(ID_PFR2_EL1, 3, 0, 0, 3, 4)\n-DEF(ID_DFR1_EL1, 3, 0, 0, 3, 5)\n-DEF(ID_MMFR5_EL1, 3, 0, 0, 3, 6)\n-DEF(CLIDR_EL1, 3, 1, 0, 0, 1)\n-DEF(ID_AA64ZFR0_EL1, 3, 0, 0, 4, 4)\n-DEF(CTR_EL0, 3, 3, 0, 0, 1)\n-DEF(DCZID_EL0, 3, 3, 0, 0, 7)\n","prefixes":["v4","02/17"]}