{"id":2231986,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2231986/?format=json","web_url":"http://patchwork.ozlabs.org/project/opensbi/patch/20260501211627.3293126-3-evvoevod@tenstorrent.com/","project":{"id":67,"url":"http://patchwork.ozlabs.org/api/1.2/projects/67/?format=json","name":"OpenSBI development","link_name":"opensbi","list_id":"opensbi.lists.infradead.org","list_email":"opensbi@lists.infradead.org","web_url":"https://github.com/riscv/opensbi","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":"https://github.com/riscv/opensbi/commit/{}"},"msgid":"<20260501211627.3293126-3-evvoevod@tenstorrent.com>","list_archive_url":null,"date":"2026-05-01T21:16:24","name":"[v2,2/5] lib: sbi: Add Smrnmi extension macros for registers and bits","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"ca606c7c0e4c1784dd1994b392b27501d18f3415","submitter":{"id":92832,"url":"http://patchwork.ozlabs.org/api/1.2/people/92832/?format=json","name":"Evgeny Voevodin","email":"evvoevod@tenstorrent.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/opensbi/patch/20260501211627.3293126-3-evvoevod@tenstorrent.com/mbox/","series":[{"id":502498,"url":"http://patchwork.ozlabs.org/api/1.2/series/502498/?format=json","web_url":"http://patchwork.ozlabs.org/project/opensbi/list/?series=502498","date":"2026-05-01T21:16:26","name":"Add RISC-V Smrnmi extension support","version":2,"mbox":"http://patchwork.ozlabs.org/series/502498/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2231986/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2231986/checks/","tags":{},"related":[],"headers":{"Return-Path":"\n ","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n secure) header.d=lists.infradead.org header.i=@lists.infradead.org\n header.a=rsa-sha256 header.s=bombadil.20210309 header.b=OWJJTwzF;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n unprotected) header.d=tenstorrent.com header.i=@tenstorrent.com\n header.a=rsa-sha256 header.s=google header.b=h2sayeL/;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=none (no SPF record) smtp.mailfrom=lists.infradead.org\n (client-ip=2607:7c80:54:3::133; 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The original\n message has been attached to this so you can view it or label\n similar future email. If you have any questions, see\n the administrator of that system for details.\n Content preview: Add CSR definitions (MNSCRATCH, MNSTATUS, MNEPC, MNCAUSE)\n and bit definitions (MNSTATUS_NMIE, MNSTATUS_MNPV, MNSTATUS_MNPP). Also add\n SBI_HART_EXT_SMRNMI to the hart extension enumeration. Signed-off-by:\n Evgeny\n Voevodin Reviewed-by: Anup Patel\n \n --- include/sbi/riscv_encoding.h | 10 ++++++++++ include/sbi/sbi_hart.h |\n 2 ++ lib/sbi/sbi_hart. [...]\n Content analysis details: (-2.1 points, 5.0 required)\n pts rule name description\n ---- ----------------------\n --------------------------------------------------\n -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no\n trust\n [2607:f8b0:4864:20:0:0:0:1233 listed in]\n [list.dnswl.org]\n -0.0 SPF_PASS SPF: sender matches SPF record\n 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record\n -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from\n envelope-from domain\n -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n author's\n domain\n 0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n not necessarily valid\n -0.1 DKIM_VALID Message has at least one valid DKIM or DK\n signature\n -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n [score: 0.0000]","X-BeenThere":"opensbi@lists.infradead.org","X-Mailman-Version":"2.1.34","Precedence":"list","List-Id":"","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"opensbi\" ","Errors-To":"opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org"},"content":"Add CSR definitions (MNSCRATCH, MNSTATUS, MNEPC, MNCAUSE) and bit definitions\n(MNSTATUS_NMIE, MNSTATUS_MNPV, MNSTATUS_MNPP). Also add SBI_HART_EXT_SMRNMI to\nthe hart extension enumeration.\n\nSigned-off-by: Evgeny Voevodin \nReviewed-by: Anup Patel \n---\n include/sbi/riscv_encoding.h | 10 ++++++++++\n include/sbi/sbi_hart.h | 2 ++\n lib/sbi/sbi_hart.c | 1 +\n 3 files changed, 13 insertions(+)","diff":"diff --git a/include/sbi/riscv_encoding.h b/include/sbi/riscv_encoding.h\nindex 3c1d5256..18f7b4a7 100644\n--- a/include/sbi/riscv_encoding.h\n+++ b/include/sbi/riscv_encoding.h\n@@ -215,6 +215,10 @@\n \n #endif\n \n+#define MNSTATUS_NMIE\t\t\t(_UL(0x8))\n+#define MNSTATUS_MNPV\t\t\t(_UL(0x80))\n+#define MNSTATUS_MNPP\t\t\t(_UL(0x1800))\n+\n #define MHPMEVENT_SSCOF_MASK\t\t_ULL(0xFF00000000000000)\n \n #define ENVCFG_STCE\t\t\t(_ULL(1) << 63)\n@@ -830,6 +834,12 @@\n #define CSR_CUSTOM10_M_RO_BASE\t\t0xFC0\n #define CSR_CUSTOM10_M_RO_COUNT\t\t0x040\n \n+/* Smrnmi extension registers */\n+#define CSR_MNSCRATCH\t\t\t\t0x740\n+#define CSR_MNEPC\t\t\t\t\t0x741\n+#define CSR_MNCAUSE\t\t\t\t\t0x742\n+#define CSR_MNSTATUS\t\t\t\t0x744\n+\n /* ===== Trap/Exception Causes ===== */\n \n #define CAUSE_MISALIGNED_FETCH\t\t0x0\ndiff --git a/include/sbi/sbi_hart.h b/include/sbi/sbi_hart.h\nindex a788b34c..937cdf29 100644\n--- a/include/sbi/sbi_hart.h\n+++ b/include/sbi/sbi_hart.h\n@@ -87,6 +87,8 @@ enum sbi_hart_extensions {\n \tSBI_HART_EXT_XSIFIVE_CFLUSH_D_L1,\n \t/** Hart has Xsfcease extension */\n \tSBI_HART_EXT_XSIFIVE_CEASE,\n+\t/** Hart has Smrnmi extension */\n+\tSBI_HART_EXT_SMRNMI,\n \n \t/** Maximum index of Hart extension */\n \tSBI_HART_EXT_MAX,\ndiff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c\nindex 99e13990..4aefb759 100644\n--- a/lib/sbi/sbi_hart.c\n+++ b/lib/sbi/sbi_hart.c\n@@ -396,6 +396,7 @@ const struct sbi_hart_ext_data sbi_hart_ext[] = {\n \t__SBI_HART_EXT_DATA(ssstateen, SBI_HART_EXT_SSSTATEEN),\n \t__SBI_HART_EXT_DATA(xsfcflushdlone, SBI_HART_EXT_XSIFIVE_CFLUSH_D_L1),\n \t__SBI_HART_EXT_DATA(xsfcease, SBI_HART_EXT_XSIFIVE_CEASE),\n+\t__SBI_HART_EXT_DATA(smrnmi, SBI_HART_EXT_SMRNMI),\n };\n \n _Static_assert(SBI_HART_EXT_MAX == array_size(sbi_hart_ext),\n","prefixes":["v2","2/5"]}