{"id":2231941,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2231941/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-gpio/patch/20260501155421.3329862-4-elder@riscstar.com/","project":{"id":42,"url":"http://patchwork.ozlabs.org/api/1.2/projects/42/?format=json","name":"Linux GPIO development","link_name":"linux-gpio","list_id":"linux-gpio.vger.kernel.org","list_email":"linux-gpio@vger.kernel.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260501155421.3329862-4-elder@riscstar.com>","list_archive_url":null,"date":"2026-05-01T15:54:11","name":"[net-next,03/12] net: pcs: pcs-xpcs: Preserve BMCR_ANENBLE during link up","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"a7707d3b0600ede6afdf3458b6f99dd33c3b1fc5","submitter":{"id":89551,"url":"http://patchwork.ozlabs.org/api/1.2/people/89551/?format=json","name":"Alex Elder","email":"elder@riscstar.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-gpio/patch/20260501155421.3329862-4-elder@riscstar.com/mbox/","series":[{"id":502478,"url":"http://patchwork.ozlabs.org/api/1.2/series/502478/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-gpio/list/?series=502478","date":"2026-05-01T15:54:09","name":"net: enable TC956x support","version":1,"mbox":"http://patchwork.ozlabs.org/series/502478/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2231941/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2231941/checks/","tags":{},"related":[],"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-gpio@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=riscstar-com.20251104.gappssmtp.com\n header.i=@riscstar-com.20251104.gappssmtp.com header.a=rsa-sha256\n header.s=20251104 header.b=Z5pLDII9;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; 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Qualcomm QPS615)\nis unable to operate at 1000base-X and slower with a PHY connected\nusing SGMII/2500base-X (in our case a Qualcomm QCA8081). The link\nnegotiates speed correctly but the MAC can't get any packets out.\n\nThis attracted attention to the ANENABLE bit and we observed that the\nbit is currently set during config and cleared during link up.\nPreserving the bit during link up allows the system to work as expected.\n\nPerhaps I lack the imagination but I couldn't come up with any reason\nwhy keeping the ANENABLE bit set would break things for other XPCS\nimplementations. Let's ensure link up sets the bit for SGMII interfaces.\n\nSigned-off-by: Daniel Thompson \nSigned-off-by: Alex Elder \n---\n drivers/net/pcs/pcs-xpcs.c | 5 ++++-\n 1 file changed, 4 insertions(+), 1 deletion(-)","diff":"diff --git a/drivers/net/pcs/pcs-xpcs.c b/drivers/net/pcs/pcs-xpcs.c\nindex b2c84b7e1e113..1d62d5b31c61c 100644\n--- a/drivers/net/pcs/pcs-xpcs.c\n+++ b/drivers/net/pcs/pcs-xpcs.c\n@@ -1263,11 +1263,14 @@ static void xpcs_link_up_sgmii_1000basex(struct dw_xpcs *xpcs,\n \t\t\t\t\t phy_interface_t interface,\n \t\t\t\t\t int speed, int duplex)\n {\n+\tu16 an_enable;\n \tint ret;\n \n \tif (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED)\n \t\treturn;\n \n+\tan_enable = (interface == PHY_INTERFACE_MODE_SGMII ? BMCR_ANENABLE : 0);\n+\n \tif (interface == PHY_INTERFACE_MODE_1000BASEX) {\n \t\tif (speed != SPEED_1000) {\n \t\t\tdev_err(&xpcs->mdiodev->dev,\n@@ -1283,7 +1286,7 @@ static void xpcs_link_up_sgmii_1000basex(struct dw_xpcs *xpcs,\n \t}\n \n \tret = xpcs_write(xpcs, MDIO_MMD_VEND2, MII_BMCR,\n-\t\t\t mii_bmcr_encode_fixed(speed, duplex));\n+\t\t\t mii_bmcr_encode_fixed(speed, duplex) | an_enable);\n \tif (ret)\n \t\tdev_err(&xpcs->mdiodev->dev, \"%s: xpcs_write returned %pe\\n\",\n \t\t\t__func__, ERR_PTR(ret));\n","prefixes":["net-next","03/12"]}