{"id":2231933,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2231933/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260501153553.66382-2-18255117159@163.com/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/1.2/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260501153553.66382-2-18255117159@163.com>","list_archive_url":null,"date":"2026-05-01T15:35:52","name":"[1/2] PCI: cadence: Ensure that cdns_pcie_host_wait_for_link() waits 100 ms after link up","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"dee1ad442c4530d3641c6a960c6ae1a489fd2cc1","submitter":{"id":89937,"url":"http://patchwork.ozlabs.org/api/1.2/people/89937/?format=json","name":"Hans Zhang","email":"18255117159@163.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260501153553.66382-2-18255117159@163.com/mbox/","series":[{"id":502476,"url":"http://patchwork.ozlabs.org/api/1.2/series/502476/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/list/?series=502476","date":"2026-05-01T15:35:53","name":"PCI: cadence: Add 100 ms delay after link up for speeds > 5 GT/s","version":1,"mbox":"http://patchwork.ozlabs.org/series/502476/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2231933/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2231933/checks/","tags":{},"related":[],"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=163.com header.i=@163.com header.a=rsa-sha256\n header.s=s110527 header.b=WqbylfZW;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; helo=sea.lore.kernel.org;\n envelope-from=linux-pci+bounces-53581-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (1024-bit key) header.d=163.com header.i=@163.com\n header.b=\"WqbylfZW\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=220.197.31.2","smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=163.com","smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=163.com"],"Received":["from sea.lore.kernel.org (sea.lore.kernel.org\n [IPv6:2600:3c0a:e001:db::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g6ZsV04jcz1y04\n\tfor ; Sat, 02 May 2026 01:37:01 +1000 (AEST)","from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sea.lore.kernel.org (Postfix) with ESMTP id 75F88302794B\n\tfor ; Fri, 1 May 2026 15:36:43 +0000 (UTC)","from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id C3A503CA499;\n\tFri, 1 May 2026 15:36:42 +0000 (UTC)","from m16.mail.163.com (m16.mail.163.com [220.197.31.2])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id 7D9282857EA;\n\tFri, 1 May 2026 15:36:37 +0000 (UTC)","from zhb.. (unknown [])\n\tby gzga-smtp-mtada-g0-3 (Coremail) with SMTP id\n _____wCH4HBbyPRpuOd_Cw--.58479S3;\n\tFri, 01 May 2026 23:35:56 +0800 (CST)"],"ARC-Seal":"i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1777649802; cv=none;\n b=DTHKsdn0CLWKtc5yLUpL1COVS13JCxa8093rWlrPlHdDuUH34icgQkwl0Il26I4BTVoeNlwEtj7+026PBU2sOiQgA5a6xfuRKLFADQh2Z6bmSuBnAxtYnJ0YS1rroiAuubGNYfyL0gEpo/lR/iWun4si4vGbrevUhKFQJXwXm0w=","ARC-Message-Signature":"i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1777649802; c=relaxed/simple;\n\tbh=KW9DC9XYLkbTx2GKpmieh0dYWCxeIawJSCek0O/je/4=;\n\th=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:\n\t MIME-Version;\n b=VoKiYAASXEhLgEXoWw6KCkPvATM4u3OF+jwpmKX02LmdEzC7K70DQTJV/lD1h6nbv0BVErJ7lkKE5qsExFYmlnSyMAePge97TvWBInSWuyiL0B4/dYxytwO8Y4TWTZUgGUJl94n+f9P/f5Gy8G2dNn6El48kGjg3vgCETMaNM9U=","ARC-Authentication-Results":"i=1; smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=163.com;\n spf=pass smtp.mailfrom=163.com;\n dkim=pass (1024-bit key) header.d=163.com header.i=@163.com\n header.b=WqbylfZW; arc=none smtp.client-ip=220.197.31.2","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com;\n\ts=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=ae\n\tBBsyJs/AzaHwhJE6ObIy2Do41KSXQFhXY0km+Aejo=; b=WqbylfZW8sxj0zm1LW\n\tEi3h8AxRJqg0USYkfCmkIZn5WVr0qEdDUA2svBjrB8XJ3GlNkoTN8boIGCRJnLTi\n\tMgE3/YtYq5V4AVTwpYTQhUGIaBO3OjGYuc/2W/hHrSKJsNwXghDx3gLhmAYowEHp\n\txAWdHF6AufquuLzoMNuFE9oKA=","From":"Hans Zhang <18255117159@163.com>","To":"bhelgaas@google.com,\n\tlpieralisi@kernel.org,\n\tkwilczynski@kernel.org,\n\tmani@kernel.org,\n\tvigneshr@ti.com","Cc":"robh@kernel.org,\n\ts-vadapalli@ti.com,\n\tlinux-omap@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org,\n\tlinux-pci@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org,\n\tHans Zhang <18255117159@163.com>","Subject":"[PATCH 1/2] PCI: cadence: Ensure that cdns_pcie_host_wait_for_link()\n waits 100 ms after link up","Date":"Fri, 1 May 2026 23:35:52 +0800","Message-Id":"<20260501153553.66382-2-18255117159@163.com>","X-Mailer":"git-send-email 2.34.1","In-Reply-To":"<20260501153553.66382-1-18255117159@163.com>","References":"<20260501153553.66382-1-18255117159@163.com>","Precedence":"bulk","X-Mailing-List":"linux-pci@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-CM-TRANSID":"_____wCH4HBbyPRpuOd_Cw--.58479S3","X-Coremail-Antispam":"1Uf129KBjvJXoWxWr15Zw4xXw1rWrWDJF4rGrg_yoW5AF4Upa\n\tyUWryfGF1xXrWY9an5A3WUXryYq3Z0ka47Jw4vgFyxWr17CrWDJFnFgF1fKFy3trsFvr13\n\tZF1DtF9rGF4avr7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2\n\t9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0pMyIUUUUUUU=","X-CM-SenderInfo":"rpryjkyvrrlimvzbiqqrwthudrp/xtbC6xzghGn0yFyuoQAA3V"},"content":"As per PCIe r6.0, sec 6.6.1, a Downstream Port that supports Link speeds\ngreater than 5.0 GT/s, software must wait a minimum of 100 ms after Link\ntraining completes before sending a Configuration Request.\n\nAdd a new 'max_link_speed' field in struct cdns_pcie to record the\nmaximum supported (or currently configured) link speed of the controller.\n\nIn cdns_pcie_host_wait_for_link(), after the link is reported as up,\ninsert a 100 ms delay if max_link_speed > 2 (i.e., > 5 GT/s). This\nimplements the required delay at the common Cadence host layer.\n\nCurrently max_link_speed is zero-initialized, so the delay is not yet\nactive. Glue drivers must set max_link_speed appropriately to enable\nthe delay. This matches the approach taken for the Synopsys DWC\ncontroller in commit 80dc18a0cba8d (\"PCI: dwc: Ensure that\ndw_pcie_wait_for_link() waits 100 ms after link up\").\n\nSigned-off-by: Hans Zhang <18255117159@163.com>\n---\n .../pci/controller/cadence/pcie-cadence-host-common.c | 9 +++++++++\n drivers/pci/controller/cadence/pcie-cadence.h | 2 ++\n 2 files changed, 11 insertions(+)","diff":"diff --git a/drivers/pci/controller/cadence/pcie-cadence-host-common.c b/drivers/pci/controller/cadence/pcie-cadence-host-common.c\nindex 2b0211870f02..d4ae762f423f 100644\n--- a/drivers/pci/controller/cadence/pcie-cadence-host-common.c\n+++ b/drivers/pci/controller/cadence/pcie-cadence-host-common.c\n@@ -14,6 +14,7 @@\n \n #include \"pcie-cadence.h\"\n #include \"pcie-cadence-host-common.h\"\n+#include \"../../pci.h\"\n \n #define LINK_RETRAIN_TIMEOUT HZ\n \n@@ -55,6 +56,14 @@ int cdns_pcie_host_wait_for_link(struct cdns_pcie *pcie,\n \t/* Check if the link is up or not */\n \tfor (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {\n \t\tif (pcie_link_up(pcie)) {\n+\t\t\t/*\n+\t\t\t * As per PCIe r6.0, sec 6.6.1, a Downstream Port that\n+\t\t\t * supports Link speeds greater than 5.0 GT/s, software\n+\t\t\t * must wait a minimum of 100 ms after Link training\n+\t\t\t * completes before sending a Configuration Request.\n+\t\t\t */\n+\t\t\tif (pcie->max_link_speed > 2)\n+\t\t\t\tmsleep(PCIE_RESET_CONFIG_WAIT_MS);\n \t\t\tdev_info(dev, \"Link up\\n\");\n \t\t\treturn 0;\n \t\t}\ndiff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h\nindex 574e9cf4d003..e222b095d2b6 100644\n--- a/drivers/pci/controller/cadence/pcie-cadence.h\n+++ b/drivers/pci/controller/cadence/pcie-cadence.h\n@@ -86,6 +86,7 @@ struct cdns_plat_pcie_of_data {\n * @ops: Platform-specific ops to control various inputs from Cadence PCIe\n * wrapper\n * @cdns_pcie_reg_offsets: Register bank offsets for different SoC\n+ * @max_link_speed: maximum supported link speed\n */\n struct cdns_pcie {\n \tvoid __iomem\t\t *reg_base;\n@@ -98,6 +99,7 @@ struct cdns_pcie {\n \tstruct device_link\t **link;\n \tconst struct cdns_pcie_ops *ops;\n \tconst struct cdns_plat_pcie_of_data *cdns_pcie_reg_offsets;\n+\tint\t\t\t\t max_link_speed;\n };\n \n /**\n","prefixes":["1/2"]}