{"id":2231932,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2231932/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260501153553.66382-3-18255117159@163.com/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/1.2/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260501153553.66382-3-18255117159@163.com>","list_archive_url":null,"date":"2026-05-01T15:35:53","name":"[2/2] PCI: j721e: Set max_link_speed to enable 100 ms delay after link up","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"2d996c4331c269a6c509bb75160cb0a0c44cbf92","submitter":{"id":89937,"url":"http://patchwork.ozlabs.org/api/1.2/people/89937/?format=json","name":"Hans Zhang","email":"18255117159@163.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260501153553.66382-3-18255117159@163.com/mbox/","series":[{"id":502476,"url":"http://patchwork.ozlabs.org/api/1.2/series/502476/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/list/?series=502476","date":"2026-05-01T15:35:53","name":"PCI: cadence: Add 100 ms delay after link up for speeds > 5 GT/s","version":1,"mbox":"http://patchwork.ozlabs.org/series/502476/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2231932/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2231932/checks/","tags":{},"related":[],"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=163.com header.i=@163.com header.a=rsa-sha256\n header.s=s110527 header.b=jhTaH9fJ;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; helo=tor.lore.kernel.org;\n envelope-from=linux-pci+bounces-53583-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (1024-bit key) header.d=163.com header.i=@163.com\n header.b=\"jhTaH9fJ\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=220.197.31.5","smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=163.com","smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=163.com"],"Received":["from tor.lore.kernel.org (tor.lore.kernel.org\n [IPv6:2600:3c04:e001:36c::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g6ZsR2XSHz1y04\n\tfor ; Sat, 02 May 2026 01:36:59 +1000 (AEST)","from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby tor.lore.kernel.org (Postfix) with ESMTP id 943EF300B577\n\tfor ; Fri, 1 May 2026 15:36:55 +0000 (UTC)","from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id AB1B63CF68A;\n\tFri, 1 May 2026 15:36:54 +0000 (UTC)","from m16.mail.163.com (m16.mail.163.com [220.197.31.5])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id 8B6233CD8C2;\n\tFri, 1 May 2026 15:36:51 +0000 (UTC)","from zhb.. (unknown [])\n\tby gzga-smtp-mtada-g0-3 (Coremail) with SMTP id\n _____wCH4HBbyPRpuOd_Cw--.58479S4;\n\tFri, 01 May 2026 23:35:57 +0800 (CST)"],"ARC-Seal":"i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1777649814; cv=none;\n b=emkCZkAzxpn9N0wwAvQw0UOBemJv0ws5KBBBaDB8g+NenvWH4YIlWCrcM5XIecrnMh5mINE1Jz8RtVw7YPOysNElDit0nDhDuOrFIjy6wTUqOwn05S1sYE7Oll13dlGTpOpEF8TrVWHHYy9e0G6h25YU37w0G7PjmUD3Oalm0/Y=","ARC-Message-Signature":"i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1777649814; c=relaxed/simple;\n\tbh=MKXEPVMRBKqTiNJKUbrmcfWXc+7QN5Gm1j7PsYVgCrs=;\n\th=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:\n\t MIME-Version;\n b=un36G8DDYmGshFvb1LVtpH6gtdzoPT/F9t/JdyY1vpMVMDU75q7YvkS0qUmdYVwF/nq+3s3iq2igpAKnIv0AJHAnKLpRaVHH//dBimqWKGqinK7X0PwZCaok0y81FuWELYSWfNELmC2nx2uNnbrMQm/4hANI2GvGKNNGIzOrNFY=","ARC-Authentication-Results":"i=1; smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=163.com;\n spf=pass smtp.mailfrom=163.com;\n dkim=pass (1024-bit key) header.d=163.com header.i=@163.com\n header.b=jhTaH9fJ; arc=none smtp.client-ip=220.197.31.5","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com;\n\ts=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=rN\n\tqbrJ0nYBLUq7KvlneyDzlxeJd5FU1yTTH99vsr+/Q=; b=jhTaH9fJuQMA7ClBan\n\t6isFXXHBF+KQZ3ULwH/LZTlMhxuWnY7b69VbtYXw1ms6DwCLoOXM16vjgN83RsO6\n\tdfEqkMGjG/a8WtVugORKCiqmWRlAo60YBNu7mEqBlJ14RzamERpp5YeywwR7g2uv\n\tsKpPj6f3psu/bmGLG7w8t0SIc=","From":"Hans Zhang <18255117159@163.com>","To":"bhelgaas@google.com,\n\tlpieralisi@kernel.org,\n\tkwilczynski@kernel.org,\n\tmani@kernel.org,\n\tvigneshr@ti.com","Cc":"robh@kernel.org,\n\ts-vadapalli@ti.com,\n\tlinux-omap@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org,\n\tlinux-pci@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org,\n\tHans Zhang <18255117159@163.com>","Subject":"[PATCH 2/2] PCI: j721e: Set max_link_speed to enable 100 ms delay\n after link up","Date":"Fri, 1 May 2026 23:35:53 +0800","Message-Id":"<20260501153553.66382-3-18255117159@163.com>","X-Mailer":"git-send-email 2.34.1","In-Reply-To":"<20260501153553.66382-1-18255117159@163.com>","References":"<20260501153553.66382-1-18255117159@163.com>","Precedence":"bulk","X-Mailing-List":"linux-pci@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-CM-TRANSID":"_____wCH4HBbyPRpuOd_Cw--.58479S4","X-Coremail-Antispam":"1Uf129KBjvJXoW7uF1xXry8try3ZF17tFy8AFb_yoW8Gr1Dpa\n\ty7GFWxG3WIqrW5uanrZ3W5XFyaqFn8J3y7GrZag3WxZFnxCr93JFyIqFyfJ3ySkF4kAF13\n\tA3Zrt342qr43tF7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2\n\t9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0zZg4U5UUUUU=","X-CM-SenderInfo":"rpryjkyvrrlimvzbiqqrwthudrp/xtbC6x3ghGn0yF2uugAA3O"},"content":"Set cdns_pcie.max_link_speed to the maximum supported link speed\n(obtained from the device tree property \"max-link-speed\") in\nj721e_pcie_set_link_speed(). This activates the post-link delay logic\nadded in cdns_pcie_host_wait_for_link() when the controller supports\nspeeds greater than 5 GT/s.\n\nAs required by PCIe r6.0 sec 6.6.1, and following the same approach as\ncommit 80dc18a0cba8d (\"PCI: dwc: Ensure that dw_pcie_wait_for_link()\nwaits 100 ms after link up\"), this ensures a 100 ms delay after link\ntraining completes before any Configuration Request is sent.\n\nSigned-off-by: Hans Zhang <18255117159@163.com>\n---\n drivers/pci/controller/cadence/pci-j721e.c | 1 +\n 1 file changed, 1 insertion(+)","diff":"diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c\nindex bfdfe98d5aba..ee85b8e04f5b 100644\n--- a/drivers/pci/controller/cadence/pci-j721e.c\n+++ b/drivers/pci/controller/cadence/pci-j721e.c\n@@ -206,6 +206,7 @@ static int j721e_pcie_set_link_speed(struct j721e_pcie *pcie,\n \t (pcie_get_link_speed(link_speed) == PCI_SPEED_UNKNOWN))\n \t\tlink_speed = 2;\n \n+\tpcie->cdns_pcie.max_link_speed = link_speed;\n \tval = link_speed - 1;\n \tret = regmap_update_bits(syscon, offset, GENERATION_SEL_MASK, val);\n \tif (ret)\n","prefixes":["2/2"]}