{"id":2231894,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2231894/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-tegra/patch/6-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com/","project":{"id":21,"url":"http://patchwork.ozlabs.org/api/1.2/projects/21/?format=json","name":"Linux Tegra Development","link_name":"linux-tegra","list_id":"linux-tegra.vger.kernel.org","list_email":"linux-tegra@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<6-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com>","list_archive_url":null,"date":"2026-05-01T14:29:15","name":"[6/9] iommu/arm-smmu-v3: Directly encode simple commands","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"03aa79c67caeb8b87ee508225e8f9012f3fdfedb","submitter":{"id":79424,"url":"http://patchwork.ozlabs.org/api/1.2/people/79424/?format=json","name":"Jason Gunthorpe","email":"jgg@nvidia.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-tegra/patch/6-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com/mbox/","series":[{"id":502465,"url":"http://patchwork.ozlabs.org/api/1.2/series/502465/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-tegra/list/?series=502465","date":"2026-05-01T14:29:09","name":"Remove SMMUv3 struct arm_smmu_cmdq_ent","version":1,"mbox":"http://patchwork.ozlabs.org/series/502465/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2231894/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2231894/checks/","tags":{},"related":[],"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-tegra@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n 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header.d=nvidia.com; arc=none"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=NAglE0Pt9QVB5x/AWVz4ctW+Z/Bn6UzRU4oo4nf/ANg=;\n b=my83klelovJKyOu5+r/IC2ZY+Hs/Qz1xBQw4kS+Uv77wOtWS4OPnS62oL57ixihTrXHEXPqAa0dXDNQawwni0MDG5noZgFuhnUzc9+k4U6rPTkIKFrpTQqNhI074c3HsTqcSuNwOUbKUJ9/rUDUhgPhrIXSfAMn19uemzK4zf+uW6cRIvzU4/MwuwaniIvjjLFRtIo6xNKJ14kDdimSXpMuSwez+4NlpQxOrv0rrjZGGItRjnCvsCpGNm2GTXdCA8Fo7thTfqMZ3oZGfEZdxPOWx9G2xTAjrwC61jSfl4Er0Gq6jzbsRnnfhNQ2cFntwvd0TbRGOM4vkWIpCHfO+Jg==","From":"Jason Gunthorpe ","To":"iommu@lists.linux.dev,\n\tJonathan Hunter ,\n\tJoerg Roedel ,\n\tlinux-arm-kernel@lists.infradead.org,\n\tlinux-tegra@vger.kernel.org,\n\tRobin Murphy ,\n\tThierry Reding ,\n\tKrishna Reddy ,\n\tWill Deacon ","Cc":"David Matlack ,\n\tPasha Tatashin ,\n\tpatches@lists.linux.dev,\n\tSamiullah Khawaja ,\n\tMostafa Saleh ","Subject":"[PATCH 6/9] iommu/arm-smmu-v3: Directly encode simple commands","Date":"Fri, 1 May 2026 11:29:15 -0300","Message-ID":"<6-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com>","In-Reply-To":"<0-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com>","References":"","Content-Transfer-Encoding":"8bit","Content-Type":"text/plain","X-ClientProxiedBy":"MN2PR05CA0001.namprd05.prod.outlook.com\n (2603:10b6:208:c0::14) To LV8PR12MB9620.namprd12.prod.outlook.com\n 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42864339-98b3-4f09-62c6-08dea78e087a","X-MS-Exchange-CrossTenant-AuthSource":"LV8PR12MB9620.namprd12.prod.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Internal","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"01 May 2026 14:29:20.8024\n (UTC)","X-MS-Exchange-CrossTenant-FromEntityHeader":"Hosted","X-MS-Exchange-CrossTenant-Id":"43083d15-7273-40c1-b7db-39efd9ccc17a","X-MS-Exchange-CrossTenant-MailboxType":"HOSTED","X-MS-Exchange-CrossTenant-UserPrincipalName":"\n A3J64A+zmtxJtbO3Y8a/HmJfOJ3QfG8ASgmQzwbXJExkiqzfTlV47Mz6A5A+SQF1","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"SA1PR12MB8096"},"content":"Add make functions to build commands for\n\n CMDQ_OP_TLBI_EL2_ALL\n CMDQ_OP_TLBI_NSNH_ALL\n CMDQ_OP_CFGI_ALL\n CMDQ_OP_PREFETCH_CFG\n CMDQ_OP_CFGI_STE\n CMDQ_OP_CFGI_CD\n CMDQ_OP_RESUME\n CMDQ_OP_PRI_RESP\n\nConvert all of these call sites to use the make function instead of\ngoing through arm_smmu_cmdq_build_cmd(). Use a #define so the general\npattern is always:\n\n arm_smmu_cmdq_issue_cmd(smmu, arm_smmu_make_cmd_XX(..));\n\nAdd arm_smmu_cmdq_batch_add_cmd() which takes struct arm_smmu_cmd\ndirectly to match the new flow.\n\nSigned-off-by: Jason Gunthorpe \n---\n drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 213 +++++++-------------\n drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 109 +++++++---\n 2 files changed, 151 insertions(+), 171 deletions(-)","diff":"diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c\nindex ef0907b1a2204f..f9c25ca9a9e7b8 100644\n--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c\n+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c\n@@ -277,23 +277,6 @@ static int arm_smmu_cmdq_build_cmd(struct arm_smmu_cmd *cmd_out,\n \tcmd[0] |= FIELD_PREP(CMDQ_0_OP, ent->opcode);\n \n \tswitch (ent->opcode) {\n-\tcase CMDQ_OP_TLBI_EL2_ALL:\n-\tcase CMDQ_OP_TLBI_NSNH_ALL:\n-\t\tbreak;\n-\tcase CMDQ_OP_PREFETCH_CFG:\n-\t\tcmd[0] |= FIELD_PREP(CMDQ_PREFETCH_0_SID, ent->prefetch.sid);\n-\t\tbreak;\n-\tcase CMDQ_OP_CFGI_CD:\n-\t\tcmd[0] |= FIELD_PREP(CMDQ_CFGI_0_SSID, ent->cfgi.ssid);\n-\t\tfallthrough;\n-\tcase CMDQ_OP_CFGI_STE:\n-\t\tcmd[0] |= FIELD_PREP(CMDQ_CFGI_0_SID, ent->cfgi.sid);\n-\t\tcmd[1] |= FIELD_PREP(CMDQ_CFGI_1_LEAF, ent->cfgi.leaf);\n-\t\tbreak;\n-\tcase CMDQ_OP_CFGI_ALL:\n-\t\t/* Cover the entire SID range */\n-\t\tcmd[1] |= FIELD_PREP(CMDQ_CFGI_1_RANGE, 31);\n-\t\tbreak;\n \tcase CMDQ_OP_TLBI_NH_VA:\n \t\tcmd[0] |= FIELD_PREP(CMDQ_TLBI_0_VMID, ent->tlbi.vmid);\n \t\tfallthrough;\n@@ -333,26 +316,6 @@ static int arm_smmu_cmdq_build_cmd(struct arm_smmu_cmd *cmd_out,\n \t\tcmd[1] |= FIELD_PREP(CMDQ_ATC_1_SIZE, ent->atc.size);\n \t\tcmd[1] |= ent->atc.addr & CMDQ_ATC_1_ADDR_MASK;\n \t\tbreak;\n-\tcase CMDQ_OP_PRI_RESP:\n-\t\tcmd[0] |= FIELD_PREP(CMDQ_0_SSV, ent->substream_valid);\n-\t\tcmd[0] |= FIELD_PREP(CMDQ_PRI_0_SSID, ent->pri.ssid);\n-\t\tcmd[0] |= FIELD_PREP(CMDQ_PRI_0_SID, ent->pri.sid);\n-\t\tcmd[1] |= FIELD_PREP(CMDQ_PRI_1_GRPID, ent->pri.grpid);\n-\t\tswitch (ent->pri.resp) {\n-\t\tcase PRI_RESP_DENY:\n-\t\tcase PRI_RESP_FAIL:\n-\t\tcase PRI_RESP_SUCC:\n-\t\t\tbreak;\n-\t\tdefault:\n-\t\t\treturn -EINVAL;\n-\t\t}\n-\t\tcmd[1] |= FIELD_PREP(CMDQ_PRI_1_RESP, ent->pri.resp);\n-\t\tbreak;\n-\tcase CMDQ_OP_RESUME:\n-\t\tcmd[0] |= FIELD_PREP(CMDQ_RESUME_0_SID, ent->resume.sid);\n-\t\tcmd[0] |= FIELD_PREP(CMDQ_RESUME_0_RESP, ent->resume.resp);\n-\t\tcmd[1] |= FIELD_PREP(CMDQ_RESUME_1_STAG, ent->resume.stag);\n-\t\tbreak;\n \tcase CMDQ_OP_CMD_SYNC:\n \t\tif (ent->sync.msiaddr) {\n \t\t\tcmd[0] |= FIELD_PREP(CMDQ_SYNC_0_CS, CMDQ_SYNC_0_CS_IRQ);\n@@ -924,25 +887,24 @@ int arm_smmu_cmdq_issue_cmdlist(struct arm_smmu_device *smmu,\n \treturn ret;\n }\n \n-static int __arm_smmu_cmdq_issue_cmd(struct arm_smmu_device *smmu,\n-\t\t\t\t struct arm_smmu_cmd *cmd,\n-\t\t\t\t bool sync)\n+static int arm_smmu_cmdq_issue_cmd_p(struct arm_smmu_device *smmu,\n+\t\t\t\t struct arm_smmu_cmd *cmd, bool sync)\n {\n \treturn arm_smmu_cmdq_issue_cmdlist(\n \t\tsmmu, arm_smmu_get_cmdq(smmu, cmd), cmd, 1, sync);\n }\n \n-static int arm_smmu_cmdq_issue_cmd(struct arm_smmu_device *smmu,\n-\t\t\t\t struct arm_smmu_cmd *cmd)\n-{\n-\treturn __arm_smmu_cmdq_issue_cmd(smmu, cmd, false);\n-}\n+#define arm_smmu_cmdq_issue_cmd(smmu, cmd) \\\n+\t({ \\\n+\t\tstruct arm_smmu_cmd __cmd = cmd; \\\n+\t\tarm_smmu_cmdq_issue_cmd_p(smmu, &__cmd, false); \\\n+\t})\n \n-static int arm_smmu_cmdq_issue_cmd_with_sync(struct arm_smmu_device *smmu,\n-\t\t\t\t\t struct arm_smmu_cmd *cmd)\n-{\n-\treturn __arm_smmu_cmdq_issue_cmd(smmu, cmd, true);\n-}\n+#define arm_smmu_cmdq_issue_cmd_with_sync(smmu, cmd) \\\n+\t({ \\\n+\t\tstruct arm_smmu_cmd __cmd = cmd; \\\n+\t\tarm_smmu_cmdq_issue_cmd_p(smmu, &__cmd, true); \\\n+\t})\n \n static void arm_smmu_cmdq_batch_init_cmd(struct arm_smmu_device *smmu,\n \t\t\t\t\t struct arm_smmu_cmdq_batch *cmds,\n@@ -962,14 +924,41 @@ static void arm_smmu_cmdq_batch_init(struct arm_smmu_device *smmu,\n \tarm_smmu_cmdq_batch_init_cmd(smmu, cmds, &cmd);\n }\n \n+static void arm_smmu_cmdq_batch_add_cmd_p(struct arm_smmu_device *smmu,\n+\t\t\t\t\t struct arm_smmu_cmdq_batch *cmds,\n+\t\t\t\t\t struct arm_smmu_cmd *cmd)\n+{\n+\tbool force_sync = (cmds->num == CMDQ_BATCH_ENTRIES - 1) &&\n+\t\t\t (smmu->options & ARM_SMMU_OPT_CMDQ_FORCE_SYNC);\n+\tbool unsupported_cmd;\n+\n+\tunsupported_cmd = !arm_smmu_cmdq_supports_cmd(cmds->cmdq, cmd);\n+\tif (force_sync || unsupported_cmd) {\n+\t\tarm_smmu_cmdq_issue_cmdlist(smmu, cmds->cmdq, cmds->cmds,\n+\t\t\t\t\t cmds->num, true);\n+\t\tarm_smmu_cmdq_batch_init_cmd(smmu, cmds, cmd);\n+\t}\n+\n+\tif (cmds->num == CMDQ_BATCH_ENTRIES) {\n+\t\tarm_smmu_cmdq_issue_cmdlist(smmu, cmds->cmdq, cmds->cmds,\n+\t\t\t\t\t cmds->num, false);\n+\t\tarm_smmu_cmdq_batch_init_cmd(smmu, cmds, cmd);\n+\t}\n+\n+\tcmds->cmds[cmds->num++] = *cmd;\n+}\n+\n+#define arm_smmu_cmdq_batch_add_cmd(smmu, cmds, cmd) \\\n+\t({ \\\n+\t\tstruct arm_smmu_cmd __cmd = cmd; \\\n+\t\tarm_smmu_cmdq_batch_add_cmd_p(smmu, cmds, &__cmd); \\\n+\t})\n+\n static void arm_smmu_cmdq_batch_add(struct arm_smmu_device *smmu,\n \t\t\t\t struct arm_smmu_cmdq_batch *cmds,\n \t\t\t\t struct arm_smmu_cmdq_ent *ent)\n {\n-\tbool force_sync = (cmds->num == CMDQ_BATCH_ENTRIES - 1) &&\n-\t\t\t (smmu->options & ARM_SMMU_OPT_CMDQ_FORCE_SYNC);\n \tstruct arm_smmu_cmd cmd;\n-\tbool unsupported_cmd;\n \n \tif (unlikely(arm_smmu_cmdq_build_cmd(&cmd, ent))) {\n \t\tdev_warn(smmu->dev, \"ignoring unknown CMDQ opcode 0x%x\\n\",\n@@ -977,20 +966,7 @@ static void arm_smmu_cmdq_batch_add(struct arm_smmu_device *smmu,\n \t\treturn;\n \t}\n \n-\tunsupported_cmd = !arm_smmu_cmdq_supports_cmd(cmds->cmdq, &cmd);\n-\tif (force_sync || unsupported_cmd) {\n-\t\tarm_smmu_cmdq_issue_cmdlist(smmu, cmds->cmdq, cmds->cmds,\n-\t\t\t\t\t cmds->num, true);\n-\t\tarm_smmu_cmdq_batch_init_cmd(smmu, cmds, &cmd);\n-\t}\n-\n-\tif (cmds->num == CMDQ_BATCH_ENTRIES) {\n-\t\tarm_smmu_cmdq_issue_cmdlist(smmu, cmds->cmdq, cmds->cmds,\n-\t\t\t\t\t cmds->num, false);\n-\t\tarm_smmu_cmdq_batch_init_cmd(smmu, cmds, &cmd);\n-\t}\n-\n-\tcmds->cmds[cmds->num++] = cmd;\n+\tarm_smmu_cmdq_batch_add_cmd_p(smmu, cmds, &cmd);\n }\n \n static int arm_smmu_cmdq_batch_submit(struct arm_smmu_device *smmu,\n@@ -1003,32 +979,29 @@ static int arm_smmu_cmdq_batch_submit(struct arm_smmu_device *smmu,\n static void arm_smmu_page_response(struct device *dev, struct iopf_fault *unused,\n \t\t\t\t struct iommu_page_response *resp)\n {\n-\tstruct arm_smmu_cmdq_ent cmd = {0};\n \tstruct arm_smmu_master *master = dev_iommu_priv_get(dev);\n-\tint sid = master->streams[0].id;\n-\tstruct arm_smmu_cmd hw_cmd;\n+\tu8 resume_resp;\n \n \tif (WARN_ON(!master->stall_enabled))\n \t\treturn;\n \n-\tcmd.opcode\t\t= CMDQ_OP_RESUME;\n-\tcmd.resume.sid\t\t= sid;\n-\tcmd.resume.stag\t\t= resp->grpid;\n \tswitch (resp->code) {\n \tcase IOMMU_PAGE_RESP_INVALID:\n \tcase IOMMU_PAGE_RESP_FAILURE:\n-\t\tcmd.resume.resp = CMDQ_RESUME_0_RESP_ABORT;\n+\t\tresume_resp = CMDQ_RESUME_0_RESP_ABORT;\n \t\tbreak;\n \tcase IOMMU_PAGE_RESP_SUCCESS:\n-\t\tcmd.resume.resp = CMDQ_RESUME_0_RESP_RETRY;\n+\t\tresume_resp = CMDQ_RESUME_0_RESP_RETRY;\n \t\tbreak;\n \tdefault:\n+\t\tresume_resp = CMDQ_RESUME_0_RESP_TERM;\n \t\tbreak;\n \t}\n \n-\tarm_smmu_cmdq_build_cmd(&hw_cmd, &cmd);\n-\tarm_smmu_cmdq_issue_cmd(master->smmu, &hw_cmd);\n-\n+\tarm_smmu_cmdq_issue_cmd(master->smmu,\n+\t\t\t\tarm_smmu_make_cmd_resume(master->streams[0].id,\n+\t\t\t\t\t\t\t resp->grpid,\n+\t\t\t\t\t\t\t resume_resp));\n \t/*\n \t * Don't send a SYNC, it doesn't do anything for RESUME or PRI_RESP.\n \t * RESUME consumption guarantees that the stalled transaction will be\n@@ -1552,19 +1525,14 @@ static void arm_smmu_sync_cd(struct arm_smmu_master *master,\n \tsize_t i;\n \tstruct arm_smmu_cmdq_batch cmds;\n \tstruct arm_smmu_device *smmu = master->smmu;\n-\tstruct arm_smmu_cmdq_ent cmd = {\n-\t\t.opcode\t= CMDQ_OP_CFGI_CD,\n-\t\t.cfgi\t= {\n-\t\t\t.ssid\t= ssid,\n-\t\t\t.leaf\t= leaf,\n-\t\t},\n-\t};\n+\tstruct arm_smmu_cmd cmd = arm_smmu_make_cmd_cfgi_cd(0, ssid, leaf);\n \n-\tarm_smmu_cmdq_batch_init(smmu, &cmds, &cmd);\n-\tfor (i = 0; i < master->num_streams; i++) {\n-\t\tcmd.cfgi.sid = master->streams[i].id;\n-\t\tarm_smmu_cmdq_batch_add(smmu, &cmds, &cmd);\n-\t}\n+\tarm_smmu_cmdq_batch_init_cmd(smmu, &cmds, &cmd);\n+\tfor (i = 0; i < master->num_streams; i++)\n+\t\tarm_smmu_cmdq_batch_add_cmd(\n+\t\t\tsmmu, &cmds,\n+\t\t\tarm_smmu_make_cmd_cfgi_cd(master->streams[i].id, ssid,\n+\t\t\t\t\t\t leaf));\n \n \tarm_smmu_cmdq_batch_submit(smmu, &cmds);\n }\n@@ -1857,17 +1825,10 @@ static void arm_smmu_ste_writer_sync_entry(struct arm_smmu_entry_writer *writer)\n {\n \tstruct arm_smmu_ste_writer *ste_writer =\n \t\tcontainer_of(writer, struct arm_smmu_ste_writer, writer);\n-\tstruct arm_smmu_cmdq_ent ent = {\n-\t\t.opcode\t= CMDQ_OP_CFGI_STE,\n-\t\t.cfgi\t= {\n-\t\t\t.sid\t= ste_writer->sid,\n-\t\t\t.leaf\t= true,\n-\t\t},\n-\t};\n-\tstruct arm_smmu_cmd cmd;\n \n-\tarm_smmu_cmdq_build_cmd(&cmd, &ent);\n-\tarm_smmu_cmdq_issue_cmd_with_sync(writer->master->smmu, &cmd);\n+\tarm_smmu_cmdq_issue_cmd_with_sync(\n+\t\twriter->master->smmu,\n+\t\tarm_smmu_make_cmd_cfgi_ste(ste_writer->sid, true));\n }\n \n static const struct arm_smmu_entry_writer_ops arm_smmu_ste_writer_ops = {\n@@ -1892,17 +1853,9 @@ static void arm_smmu_write_ste(struct arm_smmu_master *master, u32 sid,\n \tarm_smmu_write_entry(&ste_writer.writer, ste->data, target->data);\n \n \t/* It's likely that we'll want to use the new STE soon */\n-\tif (!(smmu->options & ARM_SMMU_OPT_SKIP_PREFETCH)) {\n-\t\tstruct arm_smmu_cmdq_ent\n-\t\t\tprefetch_ent = { .opcode = CMDQ_OP_PREFETCH_CFG,\n-\t\t\t\t\t .prefetch = {\n-\t\t\t\t\t\t .sid = sid,\n-\t\t\t\t\t } };\n-\t\tstruct arm_smmu_cmd prefetch_cmd;\n-\n-\t\tarm_smmu_cmdq_build_cmd(&prefetch_cmd, &prefetch_ent);\n-\t\tarm_smmu_cmdq_issue_cmd(smmu, &prefetch_cmd);\n-\t}\n+\tif (!(smmu->options & ARM_SMMU_OPT_SKIP_PREFETCH))\n+\t\tarm_smmu_cmdq_issue_cmd(smmu,\n+\t\t\t\t\tarm_smmu_make_cmd_prefetch_cfg(sid));\n }\n \n void arm_smmu_make_abort_ste(struct arm_smmu_ste *target)\n@@ -2327,22 +2280,10 @@ static void arm_smmu_handle_ppr(struct arm_smmu_device *smmu, u64 *evt)\n \t\t evt[0] & PRIQ_0_PERM_EXEC ? \"X\" : \"\",\n \t\t evt[1] & PRIQ_1_ADDR_MASK);\n \n-\tif (last) {\n-\t\tstruct arm_smmu_cmdq_ent ent = {\n-\t\t\t.opcode\t\t\t= CMDQ_OP_PRI_RESP,\n-\t\t\t.substream_valid\t= ssv,\n-\t\t\t.pri\t\t\t= {\n-\t\t\t\t.sid\t= sid,\n-\t\t\t\t.ssid\t= ssid,\n-\t\t\t\t.grpid\t= grpid,\n-\t\t\t\t.resp\t= PRI_RESP_DENY,\n-\t\t\t},\n-\t\t};\n-\t\tstruct arm_smmu_cmd cmd;\n-\n-\t\tarm_smmu_cmdq_build_cmd(&cmd, &ent);\n-\t\tarm_smmu_cmdq_issue_cmd(smmu, &cmd);\n-\t}\n+\tif (last)\n+\t\tarm_smmu_cmdq_issue_cmd(\n+\t\t\tsmmu, arm_smmu_make_cmd_pri_resp(sid, ssid, ssv, grpid,\n+\t\t\t\t\t\t\t PRI_RESP_DENY));\n }\n \n static irqreturn_t arm_smmu_priq_thread(int irq, void *dev)\n@@ -3464,7 +3405,7 @@ static void arm_smmu_inv_flush_iotlb_tag(struct arm_smmu_inv *inv)\n \n \tcmd.opcode = inv->nsize_opcode;\n \tarm_smmu_cmdq_build_cmd(&hw_cmd, &cmd);\n-\tarm_smmu_cmdq_issue_cmd_with_sync(inv->smmu, &hw_cmd);\n+\tarm_smmu_cmdq_issue_cmd_with_sync(inv->smmu, hw_cmd);\n }\n \n /* Should be installed after arm_smmu_install_ste_for_dev() */\n@@ -4827,8 +4768,6 @@ static int arm_smmu_device_reset(struct arm_smmu_device *smmu)\n {\n \tint ret;\n \tu32 reg, enables;\n-\tstruct arm_smmu_cmdq_ent ent;\n-\tstruct arm_smmu_cmd cmd;\n \n \t/* Clear CR0 and sync (disables SMMU and queue processing) */\n \treg = readl_relaxed(smmu->base + ARM_SMMU_CR0);\n@@ -4875,20 +4814,16 @@ static int arm_smmu_device_reset(struct arm_smmu_device *smmu)\n \t}\n \n \t/* Invalidate any cached configuration */\n-\tent.opcode = CMDQ_OP_CFGI_ALL;\n-\tarm_smmu_cmdq_build_cmd(&cmd, &ent);\n-\tarm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd);\n+\tarm_smmu_cmdq_issue_cmd_with_sync(smmu, arm_smmu_make_cmd_cfgi_all());\n \n \t/* Invalidate any stale TLB entries */\n \tif (smmu->features & ARM_SMMU_FEAT_HYP) {\n-\t\tent.opcode = CMDQ_OP_TLBI_EL2_ALL;\n-\t\tarm_smmu_cmdq_build_cmd(&cmd, &ent);\n-\t\tarm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd);\n+\t\tarm_smmu_cmdq_issue_cmd_with_sync(\n+\t\t\tsmmu, arm_smmu_make_cmd_op(CMDQ_OP_TLBI_EL2_ALL));\n \t}\n \n-\tent.opcode = CMDQ_OP_TLBI_NSNH_ALL;\n-\tarm_smmu_cmdq_build_cmd(&cmd, &ent);\n-\tarm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd);\n+\tarm_smmu_cmdq_issue_cmd_with_sync(\n+\t\tsmmu, arm_smmu_make_cmd_op(CMDQ_OP_TLBI_NSNH_ALL));\n \n \t/* Event queue */\n \twriteq_relaxed(smmu->evtq.q.q_base, smmu->base + ARM_SMMU_EVTQ_BASE);\ndiff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h\nindex 1fe6917448b774..10b3d95d9ee660 100644\n--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h\n+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h\n@@ -437,6 +437,12 @@ struct arm_smmu_cmd {\n #define CMDQ_PRI_1_GRPID\t\tGENMASK_ULL(8, 0)\n #define CMDQ_PRI_1_RESP\t\t\tGENMASK_ULL(13, 12)\n \n+enum pri_resp {\n+\tPRI_RESP_DENY = 0,\n+\tPRI_RESP_FAIL = 1,\n+\tPRI_RESP_SUCC = 2,\n+};\n+\n #define CMDQ_RESUME_0_RESP_TERM\t\t0UL\n #define CMDQ_RESUME_0_RESP_RETRY\t1UL\n #define CMDQ_RESUME_0_RESP_ABORT\t2UL\n@@ -475,6 +481,77 @@ enum arm_smmu_cmdq_opcode {\n \tCMDQ_OP_CMD_SYNC = 0x46,\n };\n \n+static inline struct arm_smmu_cmd\n+arm_smmu_make_cmd_op(enum arm_smmu_cmdq_opcode op)\n+{\n+\tstruct arm_smmu_cmd cmd = {};\n+\n+\tcmd.data[0] = FIELD_PREP(CMDQ_0_OP, op);\n+\treturn cmd;\n+}\n+\n+static inline struct arm_smmu_cmd arm_smmu_make_cmd_cfgi_all(void)\n+{\n+\tstruct arm_smmu_cmd cmd = arm_smmu_make_cmd_op(CMDQ_OP_CFGI_ALL);\n+\n+\tcmd.data[1] |= FIELD_PREP(CMDQ_CFGI_1_RANGE, 31);\n+\treturn cmd;\n+}\n+\n+static inline struct arm_smmu_cmd arm_smmu_make_cmd_prefetch_cfg(u32 sid)\n+{\n+\tstruct arm_smmu_cmd cmd = arm_smmu_make_cmd_op(CMDQ_OP_PREFETCH_CFG);\n+\n+\tcmd.data[0] |= FIELD_PREP(CMDQ_PREFETCH_0_SID, sid);\n+\treturn cmd;\n+}\n+\n+static inline struct arm_smmu_cmd arm_smmu_make_cmd_cfgi_ste(u32 sid, bool leaf)\n+{\n+\tstruct arm_smmu_cmd cmd = arm_smmu_make_cmd_op(CMDQ_OP_CFGI_STE);\n+\n+\tcmd.data[0] |= FIELD_PREP(CMDQ_CFGI_0_SID, sid);\n+\tcmd.data[1] |= FIELD_PREP(CMDQ_CFGI_1_LEAF, leaf);\n+\treturn cmd;\n+}\n+\n+static inline struct arm_smmu_cmd arm_smmu_make_cmd_cfgi_cd(u32 sid, u32 ssid,\n+\t\t\t\t\t\t\t bool leaf)\n+{\n+\tstruct arm_smmu_cmd cmd = arm_smmu_make_cmd_op(CMDQ_OP_CFGI_CD);\n+\n+\tcmd.data[0] |= FIELD_PREP(CMDQ_CFGI_0_SID, sid) |\n+\t\t FIELD_PREP(CMDQ_CFGI_0_SSID, ssid);\n+\tcmd.data[1] |= FIELD_PREP(CMDQ_CFGI_1_LEAF, leaf);\n+\treturn cmd;\n+}\n+\n+static inline struct arm_smmu_cmd arm_smmu_make_cmd_resume(u32 sid, u16 stag,\n+\t\t\t\t\t\t\t u8 resp)\n+{\n+\tstruct arm_smmu_cmd cmd = arm_smmu_make_cmd_op(CMDQ_OP_RESUME);\n+\n+\tcmd.data[0] |= FIELD_PREP(CMDQ_RESUME_0_SID, sid) |\n+\t\t FIELD_PREP(CMDQ_RESUME_0_RESP, resp);\n+\tcmd.data[1] |= FIELD_PREP(CMDQ_RESUME_1_STAG, stag);\n+\treturn cmd;\n+}\n+\n+static inline struct arm_smmu_cmd arm_smmu_make_cmd_pri_resp(u32 sid, u32 ssid,\n+\t\t\t\t\t\t\t bool ssv,\n+\t\t\t\t\t\t\t u16 grpid,\n+\t\t\t\t\t\t\t enum pri_resp resp)\n+{\n+\tstruct arm_smmu_cmd cmd = arm_smmu_make_cmd_op(CMDQ_OP_PRI_RESP);\n+\n+\tcmd.data[0] |= FIELD_PREP(CMDQ_0_SSV, ssv) |\n+\t\t FIELD_PREP(CMDQ_PRI_0_SID, sid) |\n+\t\t FIELD_PREP(CMDQ_PRI_0_SSID, ssid);\n+\tcmd.data[1] |= FIELD_PREP(CMDQ_PRI_1_GRPID, grpid) |\n+\t\t FIELD_PREP(CMDQ_PRI_1_RESP, resp);\n+\treturn cmd;\n+}\n+\n /* Event queue */\n #define EVTQ_ENT_SZ_SHIFT\t\t5\n #define EVTQ_ENT_DWORDS\t\t\t((1 << EVTQ_ENT_SZ_SHIFT) >> 3)\n@@ -535,12 +612,6 @@ enum arm_smmu_cmdq_opcode {\n #define MSI_IOVA_BASE\t\t\t0x8000000\n #define MSI_IOVA_LENGTH\t\t\t0x100000\n \n-enum pri_resp {\n-\tPRI_RESP_DENY = 0,\n-\tPRI_RESP_FAIL = 1,\n-\tPRI_RESP_SUCC = 2,\n-};\n-\n struct arm_smmu_cmdq_ent {\n \t/* Common fields */\n \tu8\t\t\t\topcode;\n@@ -548,19 +619,6 @@ struct arm_smmu_cmdq_ent {\n \n \t/* Command-specific fields */\n \tunion {\n-\t\tstruct {\n-\t\t\tu32\t\t\tsid;\n-\t\t} prefetch;\n-\n-\t\tstruct {\n-\t\t\tu32\t\t\tsid;\n-\t\t\tu32\t\t\tssid;\n-\t\t\tunion {\n-\t\t\t\tbool\t\tleaf;\n-\t\t\t\tu8\t\tspan;\n-\t\t\t};\n-\t\t} cfgi;\n-\n \t\tstruct {\n \t\t\tu8\t\t\tnum;\n \t\t\tu8\t\t\tscale;\n@@ -580,19 +638,6 @@ struct arm_smmu_cmdq_ent {\n \t\t\tbool\t\t\tglobal;\n \t\t} atc;\n \n-\t\tstruct {\n-\t\t\tu32\t\t\tsid;\n-\t\t\tu32\t\t\tssid;\n-\t\t\tu16\t\t\tgrpid;\n-\t\t\tenum pri_resp\t\tresp;\n-\t\t} pri;\n-\n-\t\tstruct {\n-\t\t\tu32\t\t\tsid;\n-\t\t\tu16\t\t\tstag;\n-\t\t\tu8\t\t\tresp;\n-\t\t} resume;\n-\n \t\tstruct {\n \t\t\tu64\t\t\tmsiaddr;\n \t\t} sync;\n","prefixes":["6/9"]}