{"id":2230939,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2230939/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/20260430084414.1354490-13-richard.genoud@bootlin.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/1.2/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260430084414.1354490-13-richard.genoud@bootlin.com>","list_archive_url":null,"date":"2026-04-30T08:44:05","name":"[12/20] arm: mach-k3: j721e: Enable LPM resume flow for J7200/J721e SOC","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"f4178527c07e7ea56f13fce57841e8da04093f86","submitter":{"id":88519,"url":"http://patchwork.ozlabs.org/api/1.2/people/88519/?format=json","name":"Richard Genoud (TI)","email":"richard.genoud@bootlin.com"},"delegate":{"id":3651,"url":"http://patchwork.ozlabs.org/api/1.2/users/3651/?format=json","username":"trini","first_name":"Tom","last_name":"Rini","email":"trini@ti.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/20260430084414.1354490-13-richard.genoud@bootlin.com/mbox/","series":[{"id":502237,"url":"http://patchwork.ozlabs.org/api/1.2/series/502237/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=502237","date":"2026-04-30T08:43:53","name":"Introduce resume for J7xx SoCs","version":1,"mbox":"http://patchwork.ozlabs.org/series/502237/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2230939/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2230939/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=bootlin.com header.i=@bootlin.com header.a=rsa-sha256\n header.s=dkim header.b=FRiK6a+w;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; 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a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim;\n t=1777538697; h=from:subject:date:message-id:to:cc:mime-version:\n content-transfer-encoding:in-reply-to:references;\n bh=9uTktzKFFPq1syVHDDNGnJP1gU9CNedTGFJexEHG6HQ=;\n b=FRiK6a+wJl/djiGWMFOkzHanLnbYkt9XLd8v4ncjimHIA5PNzyzAutrKxm3ZEvzzTY1MC+\n O49+Xjlpz0a4OiXCdd85a+OlLTtP6eBHSlVLTusV2XxA27bCHUUS8QzyNGuzf8yy+YE6O/\n xn/ThBSPJwJLm3uaMhsrtBKSFTJ10N98pYfPDSQ5BztoxC24RF9nKlDf8cG+eBewXHy7rW\n XMcJkC9MvuL0zMhzxNrTEqljybxxwWXm1DHhLzwyR7UI092E8EfBrTMn0dY6LbvBu2kN6+\n D4Q/zYLrqM/fL0iiwaR7tEYDR/C/BOlh6bD7ESHts0nqw9riVZDZzvPoOOSiKA==","From":"\"Richard Genoud (TI)\" ","To":"Tom Rini , Manorit Chawdhry ,\n Apurva Nandan , \"Andrew F . Davis\" ,\n Vignesh Raghavendra , Bryan Brattlof ,\n Vaishnav Achath , Jayesh Choudhary ,\n Simon Glass , Alper Nebi Yasak ","Cc":"Markus Schneider-Pargmann ,\n Udit Kumar ,\n Abhash Kumar ,\n Thomas Richard ,\n Gregory CLEMENT ,\n Thomas Petazzoni ,\n Richard Genoud , u-boot@lists.denx.de","Subject":"[PATCH 12/20] arm: mach-k3: j721e: Enable LPM resume flow for\n J7200/J721e SOC","Date":"Thu, 30 Apr 2026 10:44:05 +0200","Message-ID":"<20260430084414.1354490-13-richard.genoud@bootlin.com>","X-Mailer":"git-send-email 2.47.3","In-Reply-To":"<20260430084414.1354490-1-richard.genoud@bootlin.com>","References":"<20260430084414.1354490-1-richard.genoud@bootlin.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-Last-TLS-Session-Version":"TLSv1.3","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.39","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" ","X-Virus-Scanned":"clamav-milter 0.103.8 at phobos.denx.de","X-Virus-Status":"Clean"},"content":"From: \"Thomas Richard (TI)\" \n\nAdd support for resuming from suspend in board_init_f.\nThe resume state of the SOC is identified and lpm resume\nsequence is followed accordingly.\n\nFirst, add the board specific part of the exit retention sequence for\nk3-ddrss following the DDR resume sequence:\n - exit DDR from retention\n - de-assert the DDR_RET pin\n - restore DDR max frequency\n - exit DDR from low power\n\nThen:\n - Extract context address from devicetree and send to TIFS.\n - Power on the rproc cluster.\n - Replay the certificates attached to saved images of ATF and OPTEE.\n - Resume sequence for context restore and rproc resume.\n - Image entry to DM firmware.\n(All those steps are done in do_resume())\n\nThe context address area is firewalled by TIFS to protect it from\nother hosts.\n\nCo-developed-by: Gregory CLEMENT (TI) \nSigned-off-by: Gregory CLEMENT (TI) \nSigned-off-by: Thomas Richard (TI) \nCo-developed-by: Prasanth Babu Mantena \nSigned-off-by: Prasanth Babu Mantena \nCo-developed-by: Richard Genoud (TI) \nSigned-off-by: Richard Genoud (TI) \n---\n arch/arm/mach-k3/j721e/j721e_init.c | 64 +++++++++++++++++++++++++++++\n 1 file changed, 64 insertions(+)","diff":"diff --git a/arch/arm/mach-k3/j721e/j721e_init.c b/arch/arm/mach-k3/j721e/j721e_init.c\nindex f9af0288cf66..a1f87e653299 100644\n--- a/arch/arm/mach-k3/j721e/j721e_init.c\n+++ b/arch/arm/mach-k3/j721e/j721e_init.c\n@@ -20,9 +20,12 @@\n #include \n #include \n #include \n+#include \n+#include \n \n #include \"../sysfw-loader.h\"\n #include \"../common.h\"\n+#include \"../lpm-common.h\"\n \n /* NAVSS North Bridge (NB) registers */\n #define NAVSS0_NBSS_NB0_CFG_MMRS\t\t0x03802000\n@@ -294,10 +297,55 @@ void do_dt_magic(void)\n }\n #endif\n \n+#define GPIO_OUT_1 0x3D\n+#define DDR_RET_VAL BIT(1)\n+#define DDR_RET_CLK BIT(2)\n+#define PMIC_NSLEEP_REG 0x86\n+\n+static void __maybe_unused k3_deassert_DDR_RET(void)\n+{\n+\tstruct udevice *pmica;\n+\tstruct udevice *pmicb;\n+\tint regval;\n+\tint ret;\n+\n+\tret = uclass_get_device_by_name(UCLASS_PMIC,\n+\t\t\t\t\t\"pmic@48\", &pmica);\n+\tif (ret) {\n+\t\tprintf(\"Getting PMICA init failed: %d\\n\", ret);\n+\t\treturn;\n+\t}\n+\n+\tret = uclass_get_device_by_name(UCLASS_PMIC,\n+\t\t\t\t\t\"pmic@4c\", &pmicb);\n+\tif (ret) {\n+\t\tprintf(\"Getting PMICB init failed: %d\\n\", ret);\n+\t\treturn;\n+\t}\n+\t/* Set DDR_RET Signal Low on PMIC B */\n+\tregval = pmic_reg_read(pmicb, GPIO_OUT_1) & ~DDR_RET_VAL;\n+\n+\tpmic_reg_write(pmicb, GPIO_OUT_1, regval);\n+\n+\t/* Now toggle the CLK of the latch for DDR ret */\n+\tpmic_reg_write(pmicb, GPIO_OUT_1, regval | DDR_RET_CLK);\n+\tpmic_reg_write(pmicb, GPIO_OUT_1, regval & ~(DDR_RET_CLK));\n+\tpmic_reg_write(pmicb, GPIO_OUT_1, regval | DDR_RET_CLK);\n+\tpmic_reg_write(pmicb, GPIO_OUT_1, regval & ~(DDR_RET_CLK));\n+\n+\tpmic_reg_write(pmica, PMIC_NSLEEP_REG, 0x3);\n+}\n+\n+__weak bool j7xx_board_is_resuming(void)\n+{\n+\treturn false;\n+}\n+\n void board_init_f(ulong dummy)\n {\n \tint ret;\n #if defined(CONFIG_K3_J721E_DDRSS) || defined(CONFIG_K3_LOAD_SYSFW)\n+\tstruct k3_ddrss_regs regs;\n \tstruct udevice *dev;\n #endif\n \t/*\n@@ -410,6 +458,22 @@ void board_init_f(ulong dummy)\n \tret = uclass_get_device(UCLASS_RAM, 0, &dev);\n \tif (ret)\n \t\tpanic(\"DRAM init failed: %d\\n\", ret);\n+\n+\tif (j7xx_board_is_resuming()) {\n+\t\t/*\n+\t\t * The DDR resume sequence is:\n+\t\t * - exit DDR from retention\n+\t\t * - de-assert the DDR_RET pin\n+\t\t * - restore DDR max frequency\n+\t\t * - exit DDR from low power\n+\t\t */\n+\t\tk3_ddrss_lpddr4_exit_retention(dev, ®s);\n+\t\tk3_deassert_DDR_RET();\n+\t\tk3_ddrss_lpddr4_change_freq(dev);\n+\t\tk3_ddrss_lpddr4_exit_low_power(dev, ®s);\n+\n+\t\tdo_resume();\n+\t}\n #endif\n \tspl_enable_cache();\n \n","prefixes":["12/20"]}