{"id":2230269,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2230269/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260429143235.25115-3-farosas@suse.de/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260429143235.25115-3-farosas@suse.de>","list_archive_url":null,"date":"2026-04-29T14:32:30","name":"[PULL,2/3] tests/qtest: Add Intel IOMMU bare-metal test","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"8dbed829532993557938cdbfaab7301ba48a79f7","submitter":{"id":85343,"url":"http://patchwork.ozlabs.org/api/1.2/people/85343/?format=json","name":"Fabiano Rosas","email":"farosas@suse.de"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260429143235.25115-3-farosas@suse.de/mbox/","series":[{"id":502082,"url":"http://patchwork.ozlabs.org/api/1.2/series/502082/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502082","date":"2026-04-29T14:32:31","name":"[PULL,1/3] tests/qtest/libqos: Add Intel IOMMU helper library","version":1,"mbox":"http://patchwork.ozlabs.org/series/502082/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2230269/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2230269/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=suse.de header.i=@suse.de header.a=rsa-sha256\n header.s=susede2_rsa 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DBL_BLOCKED_OPENRESOLVER(0.00)[imap1.dmz-prg2.suse.org:helo,imap1.dmz-prg2.suse.org:rdns,suse.de:mid,suse.de:dkim,suse.de:email];\n RCVD_VIA_SMTP_AUTH(0.00)[]; TAGGED_RCPT(0.00)[];\n DKIM_TRACE(0.00)[suse.de:+]; RCPT_COUNT_THREE(0.00)[4];\n FREEMAIL_ENVRCPT(0.00)[gmail.com]","X-Rspamd-Action":"no action","X-Spam-Score":"-1.51","X-Rspamd-Server":"rspamd1.dmz-prg2.suse.org","X-Rspamd-Queue-Id":"EA6CF5BD56","Received-SPF":"pass client-ip=195.135.223.131; envelope-from=farosas@suse.de;\n helo=smtp-out2.suse.de","X-Spam_score_int":"-43","X-Spam_score":"-4.4","X-Spam_bar":"----","X-Spam_report":"(-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Fengyuan Yu <15fengyuan@gmail.com>\n\nAdd a qtest suite for the Intel IOMMU (VT-d) device on the Q35 machine.\nThe test exercises both Legacy and Scalable translation modes using\niommu-testdev and the qos-intel-iommu helpers, without requiring any\nguest kernel or firmware.\n\nThe test validates:\n- Legacy-mode Root Entry Table and Context Entry Table configuration\n- Scalable-mode Context Entry, PASID Directory, and PASID Table setup\n- Legacy-mode 4-level page table walks for 48-bit address translation\n- Scalable-mode second-level and first-level 4-level page table walks\n- Pass-through mode in both Legacy and Scalable modes\n- DMA transaction execution with memory content verification\n\nReviewed-by: Chao Liu \nSigned-off-by: Fengyuan Yu <15fengyuan@gmail.com>\nReviewed-by: Fabiano Rosas \nReviewed-by: Tao Tang \nLink: https://lore.kernel.org/qemu-devel/ce3c44f3b07734a4f0ee43f55b21c856034af1b1.1774421649.git.15fengyuan@gmail.com\nSigned-off-by: Fabiano Rosas \n---\n MAINTAINERS | 1 +\n tests/qtest/iommu-intel-test.c | 216 +++++++++++++++++++++++++++++++++\n tests/qtest/meson.build | 2 +\n 3 files changed, 219 insertions(+)\n create mode 100644 tests/qtest/iommu-intel-test.c","diff":"diff --git a/MAINTAINERS b/MAINTAINERS\nindex 3887dda851..b570c43673 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -4010,6 +4010,7 @@ F: hw/i386/intel_iommu_accel.*\n F: include/hw/i386/intel_iommu.h\n F: tests/functional/x86_64/test_intel_iommu.py\n F: tests/qtest/intel-iommu-test.c\n+F: tests/qtest/iommu-intel-test.c\n \n AMD-Vi Emulation\n M: Alejandro Jimenez \ndiff --git a/tests/qtest/iommu-intel-test.c b/tests/qtest/iommu-intel-test.c\nnew file mode 100644\nindex 0000000000..a52c45e298\n--- /dev/null\n+++ b/tests/qtest/iommu-intel-test.c\n@@ -0,0 +1,216 @@\n+/*\n+ * QTest for Intel IOMMU (VT-d) with iommu-testdev\n+ *\n+ * This QTest file is used to test the Intel IOMMU with iommu-testdev so that\n+ * we can test VT-d without any guest kernel or firmware.\n+ *\n+ * Copyright (c) 2026 Fengyuan Yu <15fengyuan@gmail.com>\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+#include \"qemu/osdep.h\"\n+#include \"libqtest.h\"\n+#include \"libqos/pci.h\"\n+#include \"libqos/pci-pc.h\"\n+#include \"hw/i386/intel_iommu_internal.h\"\n+#include \"hw/misc/iommu-testdev.h\"\n+#include \"libqos/qos-intel-iommu.h\"\n+\n+#define DMA_LEN 4\n+\n+static uint64_t intel_iommu_expected_gpa(uint64_t iova)\n+{\n+ return (QVTD_PT_VAL & VTD_PAGE_MASK_4K) + (iova & 0xfff);\n+}\n+\n+static void save_fn(QPCIDevice *dev, int devfn, void *data)\n+{\n+ QPCIDevice **pdev = (QPCIDevice **) data;\n+\n+ *pdev = dev;\n+}\n+\n+static QPCIDevice *setup_qtest_pci_device(QTestState *qts, QPCIBus **pcibus,\n+ QPCIBar *bar)\n+{\n+ QPCIDevice *dev = NULL;\n+\n+ *pcibus = qpci_new_pc(qts, NULL);\n+ g_assert(*pcibus != NULL);\n+\n+ qpci_device_foreach(*pcibus, IOMMU_TESTDEV_VENDOR_ID,\n+ IOMMU_TESTDEV_DEVICE_ID, save_fn, &dev);\n+\n+ g_assert(dev);\n+ qpci_device_enable(dev);\n+ *bar = qpci_iomap(dev, 0, NULL);\n+ g_assert_false(bar->is_io);\n+\n+ return dev;\n+}\n+\n+static const char *qvtd_iommu_args(QVTDTransMode mode)\n+{\n+ switch (mode) {\n+ case QVTD_TM_SCALABLE_FLT:\n+ return \"-device intel-iommu,x-scalable-mode=on,x-flts=on \";\n+ case QVTD_TM_SCALABLE_PT:\n+ case QVTD_TM_SCALABLE_SLT:\n+ return \"-device intel-iommu,x-scalable-mode=on \";\n+ default:\n+ return \"-device intel-iommu \";\n+ }\n+}\n+\n+static bool qvtd_check_caps(QTestState *qts, QVTDTransMode mode)\n+{\n+ uint64_t ecap = qtest_readq(qts,\n+ Q35_HOST_BRIDGE_IOMMU_ADDR + DMAR_ECAP_REG);\n+\n+ /* All scalable modes require SMTS */\n+ if (qvtd_is_scalable(mode) && !(ecap & VTD_ECAP_SMTS)) {\n+ g_test_skip(\"ECAP.SMTS not supported\");\n+ return false;\n+ }\n+\n+ switch (mode) {\n+ case QVTD_TM_SCALABLE_PT:\n+ if (!(ecap & VTD_ECAP_PT)) {\n+ g_test_skip(\"ECAP.PT not supported\");\n+ return false;\n+ }\n+ break;\n+ case QVTD_TM_SCALABLE_SLT:\n+ if (!(ecap & VTD_ECAP_SSTS)) {\n+ g_test_skip(\"ECAP.SSTS not supported\");\n+ return false;\n+ }\n+ break;\n+ case QVTD_TM_SCALABLE_FLT:\n+ if (!(ecap & VTD_ECAP_FSTS)) {\n+ g_test_skip(\"ECAP.FSTS not supported\");\n+ return false;\n+ }\n+ break;\n+ default:\n+ break;\n+ }\n+\n+ return true;\n+}\n+\n+static void run_intel_iommu_translation(const QVTDTestConfig *cfg)\n+{\n+ QTestState *qts;\n+ QPCIBus *pcibus;\n+ QPCIDevice *dev;\n+ QPCIBar bar;\n+\n+ if (!qtest_has_machine(\"q35\")) {\n+ g_test_skip(\"q35 machine not available\");\n+ return;\n+ }\n+\n+ /* Initialize QEMU environment for Intel IOMMU testing */\n+ qts = qtest_initf(\"-machine q35 -smp 1 -m 512 -net none \"\n+ \"%s -device iommu-testdev\",\n+ qvtd_iommu_args(cfg->trans_mode));\n+\n+ /* Check CAP/ECAP capabilities for required translation mode */\n+ if (!qvtd_check_caps(qts, cfg->trans_mode)) {\n+ qtest_quit(qts);\n+ return;\n+ }\n+\n+ /* Setup and configure IOMMU-testdev PCI device */\n+ dev = setup_qtest_pci_device(qts, &pcibus, &bar);\n+ g_assert(dev);\n+\n+ g_test_message(\"### Intel IOMMU translation mode=%d ###\", cfg->trans_mode);\n+ qvtd_run_translation_case(qts, dev, bar, Q35_HOST_BRIDGE_IOMMU_ADDR, cfg);\n+ g_free(dev);\n+ qpci_free_pc(pcibus);\n+ qtest_quit(qts);\n+}\n+\n+static void test_intel_iommu_legacy_pt(void)\n+{\n+ QVTDTestConfig cfg = {\n+ .trans_mode = QVTD_TM_LEGACY_PT,\n+ .dma_gpa = QVTD_IOVA, /* pass-through: GPA == IOVA */\n+ .dma_len = DMA_LEN,\n+ .expected_result = 0,\n+ };\n+\n+ run_intel_iommu_translation(&cfg);\n+}\n+\n+static void test_intel_iommu_legacy_trans(void)\n+{\n+ QVTDTestConfig cfg = {\n+ .trans_mode = QVTD_TM_LEGACY_TRANS,\n+ .dma_gpa = intel_iommu_expected_gpa(QVTD_IOVA),\n+ .dma_len = DMA_LEN,\n+ .expected_result = 0,\n+ };\n+\n+ run_intel_iommu_translation(&cfg);\n+}\n+\n+static void test_intel_iommu_scalable_pt(void)\n+{\n+ QVTDTestConfig cfg = {\n+ .trans_mode = QVTD_TM_SCALABLE_PT,\n+ .dma_gpa = QVTD_IOVA, /* pass-through: GPA == IOVA */\n+ .dma_len = DMA_LEN,\n+ .expected_result = 0,\n+ };\n+\n+ run_intel_iommu_translation(&cfg);\n+}\n+\n+static void test_intel_iommu_scalable_slt(void)\n+{\n+ QVTDTestConfig cfg = {\n+ .trans_mode = QVTD_TM_SCALABLE_SLT,\n+ .dma_gpa = intel_iommu_expected_gpa(QVTD_IOVA),\n+ .dma_len = DMA_LEN,\n+ .expected_result = 0,\n+ };\n+\n+ run_intel_iommu_translation(&cfg);\n+}\n+\n+static void test_intel_iommu_scalable_flt(void)\n+{\n+ QVTDTestConfig cfg = {\n+ .trans_mode = QVTD_TM_SCALABLE_FLT,\n+ .dma_gpa = intel_iommu_expected_gpa(QVTD_IOVA),\n+ .dma_len = DMA_LEN,\n+ .expected_result = 0,\n+ };\n+\n+ run_intel_iommu_translation(&cfg);\n+}\n+\n+int main(int argc, char **argv)\n+{\n+ g_test_init(&argc, &argv, NULL);\n+\n+ /* Legacy mode tests */\n+ qtest_add_func(\"/iommu-testdev/intel/legacy-pt\",\n+ test_intel_iommu_legacy_pt);\n+ qtest_add_func(\"/iommu-testdev/intel/legacy-trans\",\n+ test_intel_iommu_legacy_trans);\n+\n+ /* Scalable mode tests */\n+ qtest_add_func(\"/iommu-testdev/intel/scalable-pt\",\n+ test_intel_iommu_scalable_pt);\n+ qtest_add_func(\"/iommu-testdev/intel/scalable-slt\",\n+ test_intel_iommu_scalable_slt);\n+ qtest_add_func(\"/iommu-testdev/intel/scalable-flt\",\n+ test_intel_iommu_scalable_flt);\n+\n+ return g_test_run();\n+}\ndiff --git a/tests/qtest/meson.build b/tests/qtest/meson.build\nindex b735f55fc4..43f83ffd3a 100644\n--- a/tests/qtest/meson.build\n+++ b/tests/qtest/meson.build\n@@ -96,6 +96,8 @@ qtests_i386 = \\\n (config_all_devices.has_key('CONFIG_SDHCI_PCI') ? ['fuzz-sdcard-test'] : []) + \\\n (config_all_devices.has_key('CONFIG_ESP_PCI') ? ['am53c974-test'] : []) + \\\n (config_all_devices.has_key('CONFIG_VTD') ? ['intel-iommu-test'] : []) + \\\n+ (config_all_devices.has_key('CONFIG_VTD') and\n+ config_all_devices.has_key('CONFIG_IOMMU_TESTDEV') ? ['iommu-intel-test'] : []) + \\\n (host_os != 'windows' and \\\n config_all_devices.has_key('CONFIG_ACPI_ERST') ? ['erst-test'] : []) + \\\n (config_all_devices.has_key('CONFIG_PCIE_PORT') and \\\n","prefixes":["PULL","2/3"]}