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0790acd2-1232-42bb-cf61-08dea5d5e40c","X-MS-Exchange-CrossTenant-AuthSource":"AM0PR04MB7044.eurprd04.prod.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Internal","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"29 Apr 2026 09:58:40.6828\n (UTC)","X-MS-Exchange-CrossTenant-FromEntityHeader":"Hosted","X-MS-Exchange-CrossTenant-Id":"686ea1d3-bc2b-4c6f-a92c-d99c5c301635","X-MS-Exchange-CrossTenant-MailboxType":"HOSTED","X-MS-Exchange-CrossTenant-UserPrincipalName":"\n tQxogmjYWFvniVQe/ubYf3eYrFOg2Cg+9iVkRqFAl7rTq8Wf+6c4F3HbZfKmEyLZomGw3fgQ8Et8jKmaOwRlcA==","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"PAXPR04MB8269","X-Spam-Status":"No, score=0.8 required=3.0 tests=ARC_SIGNED,ARC_VALID,\n\tDKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO,\n\tSPF_HELO_PASS,T_SPF_PERMERROR autolearn=disabled version=4.0.1 OzLabs 8","X-Spam-Checker-Version":"SpamAssassin 4.0.1 (2024-03-25) on lists.ozlabs.org"},"content":"The CS42888 codec has 4 I2S lanes with 2 channels per lane. Using odd\nchannel counts (3, 5, 7) causes data misalignment in the I2S frame,\nresulting in incorrect channel mapping. Only mono and even channel\ncounts (1, 2, 4, 6, 8) work correctly.\n\nAdditionally, the fixed system clock on i.MX platforms limits supported\nsample rates. With 12.288 MHz MCLK, only 48kHz family rates (48k, 96k,\n192k) achieve valid MCLK:LRCK ratios. With 11.2896 MHz MCLK, only 44k\nfamily rates are supported.\n\nAdd a startup callback to apply PCM constraints for both channels and\nrates, preventing userspace from requesting unsupported configurations.\n\nSigned-off-by: Shengjiu Wang \n---\n sound/soc/fsl/fsl-asoc-card.c | 71 +++++++++++++++++++++++++++++++++++\n 1 file changed, 71 insertions(+)","diff":"diff --git a/sound/soc/fsl/fsl-asoc-card.c b/sound/soc/fsl/fsl-asoc-card.c\nindex e08e135886f7..90414ac10032 100644\n--- a/sound/soc/fsl/fsl-asoc-card.c\n+++ b/sound/soc/fsl/fsl-asoc-card.c\n@@ -40,6 +40,33 @@\n /* Default DAI format without Master and Slave flag */\n #define DAI_FMT_BASE (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF)\n \n+static const u32 cs42888_rates_48k[] = {\n+\t48000, 96000, 192000,\n+};\n+\n+static const u32 cs42888_rates_44k[] = {\n+\t44100, 88200, 176400,\n+};\n+\n+static const u32 cs42888_channels[] = {\n+\t1, 2, 4, 6, 8,\n+};\n+\n+static const struct snd_pcm_hw_constraint_list cs42888_rate_48k_constraints = {\n+\t.list = cs42888_rates_48k,\n+\t.count = ARRAY_SIZE(cs42888_rates_48k),\n+};\n+\n+static const struct snd_pcm_hw_constraint_list cs42888_rate_44k_constraints = {\n+\t.list = cs42888_rates_44k,\n+\t.count = ARRAY_SIZE(cs42888_rates_44k),\n+};\n+\n+static const struct snd_pcm_hw_constraint_list cs42888_channel_constraints = {\n+\t.list = cs42888_channels,\n+\t.count = ARRAY_SIZE(cs42888_channels),\n+};\n+\n /**\n * struct codec_priv - CODEC private data\n * @mclk: Main clock of the CODEC\n@@ -87,6 +114,8 @@ struct cpu_priv {\n * @codec_priv: CODEC private data\n * @cpu_priv: CPU private data\n * @card: ASoC card structure\n+ * @constraint_rates: array of supported rates\n+ * @constraint_channels: array of supported channels\n * @streams: Mask of current active streams\n * @sample_rate: Current sample rate\n * @sample_format: Current sample format\n@@ -104,6 +133,8 @@ struct fsl_asoc_card_priv {\n \tstruct codec_priv codec_priv[2];\n \tstruct cpu_priv cpu_priv;\n \tstruct snd_soc_card card;\n+\tconst struct snd_pcm_hw_constraint_list *constraint_rates;\n+\tconst struct snd_pcm_hw_constraint_list *constraint_channels;\n \tu8 streams;\n \tu32 sample_rate;\n \tsnd_pcm_format_t sample_format;\n@@ -291,7 +322,39 @@ static int fsl_asoc_card_hw_free(struct snd_pcm_substream *substream)\n \treturn 0;\n }\n \n+static int fsl_asoc_card_startup(struct snd_pcm_substream *substream)\n+{\n+\tstruct snd_soc_pcm_runtime *rtd = substream->private_data;\n+\tstruct fsl_asoc_card_priv *priv = snd_soc_card_get_drvdata(rtd->card);\n+\tstruct snd_pcm_runtime *runtime = substream->runtime;\n+\tint ret;\n+\n+\tif (priv->constraint_channels) {\n+\t\tret = snd_pcm_hw_constraint_list(runtime, 0,\n+\t\t\t\t\t\t SNDRV_PCM_HW_PARAM_CHANNELS,\n+\t\t\t\t\t\t priv->constraint_channels);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t}\n+\n+\t/*\n+\t * Apply rate constraints only to frontend DAI links (no_pcm = 0).\n+\t * Skip DPCM backend (no_pcm = 1) as rate is fixed by be_hw_params_fixup()\n+\t * and ASRC frontend handles rate conversion.\n+\t */\n+\tif (priv->constraint_rates && !rtd->dai_link->no_pcm) {\n+\t\tret = snd_pcm_hw_constraint_list(runtime, 0,\n+\t\t\t\t\t\t SNDRV_PCM_HW_PARAM_RATE,\n+\t\t\t\t\t\t priv->constraint_rates);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n static const struct snd_soc_ops fsl_asoc_card_ops = {\n+\t.startup = fsl_asoc_card_startup,\n \t.hw_params = fsl_asoc_card_hw_params,\n \t.hw_free = fsl_asoc_card_hw_free,\n };\n@@ -753,6 +816,14 @@ static int fsl_asoc_card_probe(struct platform_device *pdev)\n \t\tpriv->cpu_priv.sysclk_dir[RX] = SND_SOC_CLOCK_OUT;\n \t\tpriv->cpu_priv.slot_width = 32;\n \t\tpriv->dai_fmt |= SND_SOC_DAIFMT_CBC_CFC;\n+\t\tpriv->constraint_channels = &cs42888_channel_constraints;\n+\t\tif (priv->codec_priv[0].mclk_freq % 12288000 == 0)\n+\t\t\tpriv->constraint_rates = &cs42888_rate_48k_constraints;\n+\t\telse if (priv->codec_priv[0].mclk_freq % 11289600 == 0)\n+\t\t\tpriv->constraint_rates = &cs42888_rate_44k_constraints;\n+\t\telse\n+\t\t\tdev_warn(&pdev->dev, \"Unknown MCLK frequency %lu, no rate constraints\\n\",\n+\t\t\t\t priv->codec_priv[0].mclk_freq);\n \t} else if (of_device_is_compatible(np, \"fsl,imx-audio-cs427x\")) {\n \t\tcodec_dai_name[0] = \"cs4271-hifi\";\n \t\tpriv->codec_priv[0].mclk_id = CS427x_SYSCLK_MCLK;\n","prefixes":["v2","3/5"]}