{"id":2228554,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2228554/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260427-ultrarisc-pcie-v4-3-98935f6cdfb5@ultrarisc.com/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/1.2/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260427-ultrarisc-pcie-v4-3-98935f6cdfb5@ultrarisc.com>","list_archive_url":null,"date":"2026-04-27T01:32:12","name":"[v4,3/3] PCI: ultrarisc: Add UltraRISC DP1000 PCIe Root Complex driver","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"0233b5ea11625bbabf5e53533661fab09744d421","submitter":{"id":92886,"url":"http://patchwork.ozlabs.org/api/1.2/people/92886/?format=json","name":"Jia Wang","email":"wangjia@ultrarisc.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260427-ultrarisc-pcie-v4-3-98935f6cdfb5@ultrarisc.com/mbox/","series":[{"id":501558,"url":"http://patchwork.ozlabs.org/api/1.2/series/501558/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/list/?series=501558","date":"2026-04-27T01:32:09","name":"riscv: Add PCIe support for UltraRISC DP1000 SoC","version":4,"mbox":"http://patchwork.ozlabs.org/series/501558/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2228554/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2228554/checks/","tags":{},"related":[],"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=ultrarisc.com header.i=@ultrarisc.com\n header.a=rsa-sha256 header.s=dkim header.b=LhJQWT+G;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; 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charset=\"utf-8\"","Content-Transfer-Encoding":"7bit","Message-Id":"<20260427-ultrarisc-pcie-v4-3-98935f6cdfb5@ultrarisc.com>","References":"<20260427-ultrarisc-pcie-v4-0-98935f6cdfb5@ultrarisc.com>","In-Reply-To":"<20260427-ultrarisc-pcie-v4-0-98935f6cdfb5@ultrarisc.com>","To":"Paul Walmsley , Palmer Dabbelt ,\n Albert Ou , Alexandre Ghiti ,\n Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?=\n\t=?utf-8?q?=C5=84ski?= ,\n Manivannan Sadhasivam , Rob Herring ,\n Bjorn Helgaas , Jingoo Han ,\n Xincheng Zhang ,\n Krzysztof Kozlowski ,\n Conor Dooley ","Cc":"linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,\n linux-pci@vger.kernel.org, devicetree@vger.kernel.org,\n Jia Wang ","X-Mailer":"b4 0.15-dev","X-Developer-Signature":"v=1; a=ed25519-sha256; t=1777253539; l=9133;\n i=wangjia@ultrarisc.com; s=20260309; h=from:subject:message-id;\n bh=pEEmEszYk+Wwemr9LH9I5Z0OFr07mXJ55nbPQpUoxLw=;\n b=kHFtH1VZanxix+cZOxd643Wi5ZsvL2zlmni3SZJZgSTUdHya3UXdCw8DVnQUVVNNGMIG55cAY\n cQqXkJVpeAMD01/Nk1aGjYl+2hjJ2JEf5xjWVMoTzfn/8NJw7WHJRi4","X-Developer-Key":"i=wangjia@ultrarisc.com; a=ed25519;\n pk=XvYkrelqJIIzobY7j+nIg8rsfv5kzaOzuc1UPhd087U=","X-CM-TRANSID":"AQAAfwA3cULPvO5ps_0CAA--.1758S5","X-Coremail-Antispam":"1UD129KBjvJXoW3JFyktr4fuF47Gry5JrWfuFg_yoWfZFykpa\n\t15CFWFyF4UJF45ua1Skas5uF1aq3ZxArWUGa9Fgw1293ZxAryUXFyvq34ayFn7GF4UWrya\n\tkw1jya4UGa15XwUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2\n\t9KBjDU0xBIdaVrnUUvcSsGvfC2KfnxnUUI43ZEXa7xR_UUUUUUUUU==","X-CM-SenderInfo":"pzdqwylld63zxwud2x1vfou0bp/1tbiAQAKEWnti78ACQAAsj"},"content":"From: Xincheng Zhang \n\nAdd DP1000 SoC PCIe Root Complex driver.\n\nThe controller only supports 32-bit aligned configuration space accesses.\n\nSigned-off-by: Xincheng Zhang \nSigned-off-by: Jia Wang \n---\n MAINTAINERS | 1 +\n drivers/pci/controller/dwc/Kconfig | 12 ++\n drivers/pci/controller/dwc/Makefile | 1 +\n drivers/pci/controller/dwc/pcie-designware.h | 22 ++++\n drivers/pci/controller/dwc/pcie-ultrarisc.c | 175 +++++++++++++++++++++++++++\n 5 files changed, 211 insertions(+)","diff":"diff --git a/MAINTAINERS b/MAINTAINERS\nindex 818685933541..16203b804c16 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -20589,6 +20589,7 @@ M:\tJia Wang \n L:\tlinux-pci@vger.kernel.org\n S:\tMaintained\n F:\tDocumentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml\n+F:\tdrivers/pci/controller/dwc/pcie-ultrarisc.c\n \n PCIE ENDPOINT DRIVER FOR QUALCOMM\n M:\tManivannan Sadhasivam \ndiff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig\nindex d0aa031397fa..06f7d98259cd 100644\n--- a/drivers/pci/controller/dwc/Kconfig\n+++ b/drivers/pci/controller/dwc/Kconfig\n@@ -548,4 +548,16 @@ config PCIE_VISCONTI_HOST\n \t Say Y here if you want PCIe controller support on Toshiba Visconti SoC.\n \t This driver supports TMPV7708 SoC.\n \n+config PCIE_ULTRARISC\n+\ttristate \"UltraRISC PCIe host controller\"\n+\tdepends on ARCH_ULTRARISC || COMPILE_TEST\n+\tselect PCIE_DW_HOST\n+\tselect PCI_MSI\n+\tdefault y if ARCH_ULTRARISC\n+\thelp\n+\t Enables support for the PCIe controller in the UltraRISC SoC.\n+\t This driver supports UR-DP1000 SoC.\n+\t By default, this symbol is enabled when ARCH_ULTRARISC is active,\n+\t requiring no further configuration on that platform.\n+\n endmenu\ndiff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile\nindex 67ba59c02038..884c46b78e01 100644\n--- a/drivers/pci/controller/dwc/Makefile\n+++ b/drivers/pci/controller/dwc/Makefile\n@@ -38,6 +38,7 @@ obj-$(CONFIG_PCIE_RCAR_GEN4) += pcie-rcar-gen4.o\n obj-$(CONFIG_PCIE_SPACEMIT_K1) += pcie-spacemit-k1.o\n obj-$(CONFIG_PCIE_STM32_HOST) += pcie-stm32.o\n obj-$(CONFIG_PCIE_STM32_EP) += pcie-stm32-ep.o\n+obj-$(CONFIG_PCIE_ULTRARISC) += pcie-ultrarisc.o\n \n # The following drivers are for devices that use the generic ACPI\n # pci_root.c driver but don't support standard ECAM config access.\ndiff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h\nindex ae6389dd9caa..88dcb0e7943a 100644\n--- a/drivers/pci/controller/dwc/pcie-designware.h\n+++ b/drivers/pci/controller/dwc/pcie-designware.h\n@@ -69,6 +69,8 @@\n \n /* Synopsys-specific PCIe configuration registers */\n #define PCIE_PORT_FORCE\t\t\t0x708\n+/* Bit[7:0] LINK_NUM: Link Number. Not used for endpoint */\n+#define PORT_LINK_NUM_MASK\t\tGENMASK(7, 0)\n #define PORT_FORCE_DO_DESKEW_FOR_SRIS\tBIT(23)\n \n #define PCIE_PORT_AFR\t\t\t0x70C\n@@ -96,6 +98,26 @@\n #define PCIE_PORT_LANE_SKEW\t\t0x714\n #define PORT_LANE_SKEW_INSERT_MASK\tGENMASK(23, 0)\n \n+/*\n+ * PCIE_TIMER_CTRL_MAX_FUNC_NUM: Timer Control and Max Function Number\n+ * Register.\n+ * This register holds the ack frequency, latency, replay, fast link\n+ * scaling timers, and max function number values.\n+ * Bit[30:29] FAST_LINK_SCALING_FACTOR: Fast Link Timer Scaling Factor.\n+ * 0x0 (SF_1024):Scaling Factor is 1024 (1ms is 1us).\n+ * When the LTSSM is in Config or L12 Entry State, 1ms\n+ * timer is 2us, 2ms timer is 4us and 3ms timer is 6us.\n+ * 0x1 (SF_256): Scaling Factor is 256 (1ms is 4us)\n+ * 0x2 (SF_64): Scaling Factor is 64 (1ms is 16us)\n+ * 0x3 (SF_16): Scaling Factor is 16 (1ms is 64us)\n+ */\n+#define PCIE_TIMER_CTRL_MAX_FUNC_NUM\t0x718\n+#define PORT_FLT_SF_MASK\tGENMASK(30, 29)\n+#define PORT_FLT_SF_VAL_1024\t0x0\n+#define PORT_FLT_SF_VAL_256\t0x1\n+#define PORT_FLT_SF_VAL_64\t0x2\n+#define PORT_FLT_SF_VAL_16\t0x3\n+\n #define PCIE_PORT_DEBUG0\t\t0x728\n #define PORT_LOGIC_LTSSM_STATE_MASK\t0x3f\n #define PORT_LOGIC_LTSSM_STATE_L0\t0x11\ndiff --git a/drivers/pci/controller/dwc/pcie-ultrarisc.c b/drivers/pci/controller/dwc/pcie-ultrarisc.c\nnew file mode 100644\nindex 000000000000..7326bd446590\n--- /dev/null\n+++ b/drivers/pci/controller/dwc/pcie-ultrarisc.c\n@@ -0,0 +1,175 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * DWC PCIe RC driver for UltraRISC SoCs\n+ *\n+ * Copyright (C) 2026 UltraRISC Technology (Shanghai) Co., Ltd.\n+ */\n+\n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+\n+#include \"pcie-designware.h\"\n+\n+#define PCIE_CUS_CORE 0x400000\n+\n+#define LTSSM_ENABLE BIT(7)\n+#define FAST_LINK_MODE BIT(12)\n+#define HOLD_PHY_RST BIT(14)\n+#define L1SUB_DISABLE BIT(15)\n+\n+#define ULTRARISC_PCIE_COMP_TIMEOUT_65_210MS\t0x6\n+\n+static struct pci_ops ultrarisc_pci_ops = {\n+\t.map_bus = dw_pcie_own_conf_map_bus,\n+\t.read = pci_generic_config_read32,\n+\t.write = pci_generic_config_write32,\n+};\n+\n+static int ultrarisc_pcie_host_init(struct dw_pcie_rp *pp)\n+{\n+\tstruct dw_pcie *pci = to_dw_pcie_from_pp(pp);\n+\tstruct pci_host_bridge *bridge = pp->bridge;\n+\tu8 cap_exp;\n+\tu32 val;\n+\n+\tbridge->ops = &ultrarisc_pci_ops;\n+\n+\tif (dw_pcie_link_up(pci))\n+\t\treturn 0;\n+\n+\tval = dw_pcie_readl_dbi(pci, PCIE_CUS_CORE);\n+\tval &= ~FAST_LINK_MODE;\n+\tdw_pcie_writel_dbi(pci, PCIE_CUS_CORE, val);\n+\n+\tval = dw_pcie_readl_dbi(pci, PCIE_TIMER_CTRL_MAX_FUNC_NUM);\n+\tFIELD_MODIFY(PORT_FLT_SF_MASK, &val, PORT_FLT_SF_VAL_64);\n+\tdw_pcie_writel_dbi(pci, PCIE_TIMER_CTRL_MAX_FUNC_NUM, val);\n+\n+\tcap_exp = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);\n+\tval = dw_pcie_readl_dbi(pci, cap_exp + PCI_EXP_LNKCTL2);\n+\tFIELD_MODIFY(PCI_EXP_LNKCTL2_TLS, &val, PCI_EXP_LNKCTL2_TLS_16_0GT);\n+\tdw_pcie_writel_dbi(pci, cap_exp + PCI_EXP_LNKCTL2, val);\n+\n+\tval = dw_pcie_readl_dbi(pci, PCIE_PORT_FORCE);\n+\tFIELD_MODIFY(PORT_LINK_NUM_MASK, &val, 0);\n+\tdw_pcie_writel_dbi(pci, PCIE_PORT_FORCE, val);\n+\n+\tval = dw_pcie_readl_dbi(pci, cap_exp + PCI_EXP_DEVCTL2);\n+\tFIELD_MODIFY(PCI_EXP_DEVCTL2_COMP_TIMEOUT, &val,\n+\t\t ULTRARISC_PCIE_COMP_TIMEOUT_65_210MS);\n+\tdw_pcie_writel_dbi(pci, cap_exp + PCI_EXP_DEVCTL2, val);\n+\n+\tval = dw_pcie_readl_dbi(pci, PCIE_CUS_CORE);\n+\tval &= ~(HOLD_PHY_RST | L1SUB_DISABLE);\n+\tdw_pcie_writel_dbi(pci, PCIE_CUS_CORE, val);\n+\n+\treturn 0;\n+}\n+\n+static void ultrarisc_pcie_pme_turn_off(struct dw_pcie_rp *pp)\n+{\n+\t/*\n+\t * DP1000 does not support sending PME_Turn_Off from the RC.\n+\t * Keep this callback empty to skip the generic MSG TLP path.\n+\t */\n+}\n+\n+static const struct dw_pcie_host_ops ultrarisc_pcie_host_ops = {\n+\t.init = ultrarisc_pcie_host_init,\n+\t.pme_turn_off = ultrarisc_pcie_pme_turn_off,\n+};\n+\n+static int ultrarisc_pcie_start_link(struct dw_pcie *pci)\n+{\n+\tu32 val;\n+\n+\tval = dw_pcie_readl_dbi(pci, PCIE_CUS_CORE);\n+\tval |= LTSSM_ENABLE;\n+\tdw_pcie_writel_dbi(pci, PCIE_CUS_CORE, val);\n+\n+\treturn 0;\n+}\n+\n+static const struct dw_pcie_ops dw_pcie_ops = {\n+\t.start_link = ultrarisc_pcie_start_link,\n+};\n+\n+static int ultrarisc_pcie_probe(struct platform_device *pdev)\n+{\n+\tstruct device *dev = &pdev->dev;\n+\tstruct dw_pcie_rp *pp;\n+\tstruct dw_pcie *pci;\n+\tint ret;\n+\n+\tpci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);\n+\tif (!pci)\n+\t\treturn -ENOMEM;\n+\n+\tpci->dev = dev;\n+\tpci->ops = &dw_pcie_ops;\n+\n+\t/* Set a default value suitable for at most 16 in and 16 out windows */\n+\tpci->atu_size = SZ_8K;\n+\n+\tpp = &pci->pp;\n+\n+\tplatform_set_drvdata(pdev, pci);\n+\n+\tpp->num_vectors = MAX_MSI_IRQS;\n+\t/* No L2/L3 Ready indication is available on this platform. */\n+\tpp->skip_l23_ready = true;\n+\tpp->ops = &ultrarisc_pcie_host_ops;\n+\n+\tret = dw_pcie_host_init(pp);\n+\tif (ret) {\n+\t\tdev_err(dev, \"Failed to initialize host\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int ultrarisc_pcie_suspend_noirq(struct device *dev)\n+{\n+\tstruct dw_pcie *pci = dev_get_drvdata(dev);\n+\n+\treturn dw_pcie_suspend_noirq(pci);\n+}\n+\n+static int ultrarisc_pcie_resume_noirq(struct device *dev)\n+{\n+\tstruct dw_pcie *pci = dev_get_drvdata(dev);\n+\n+\treturn dw_pcie_resume_noirq(pci);\n+}\n+\n+static const struct dev_pm_ops ultrarisc_pcie_pm_ops = {\n+\tNOIRQ_SYSTEM_SLEEP_PM_OPS(ultrarisc_pcie_suspend_noirq,\n+\t\t\t\t ultrarisc_pcie_resume_noirq)\n+};\n+\n+static const struct of_device_id ultrarisc_pcie_of_match[] = {\n+\t{\n+\t\t.compatible = \"ultrarisc,dp1000-pcie\",\n+\t},\n+\t{},\n+};\n+MODULE_DEVICE_TABLE(of, ultrarisc_pcie_of_match);\n+\n+static struct platform_driver ultrarisc_pcie_driver = {\n+\t.driver = {\n+\t\t.name\t= \"ultrarisc-pcie\",\n+\t\t.of_match_table = ultrarisc_pcie_of_match,\n+\t\t.suppress_bind_attrs = true,\n+\t\t.pm = &ultrarisc_pcie_pm_ops,\n+\t},\n+\t.probe = ultrarisc_pcie_probe,\n+};\n+module_platform_driver(ultrarisc_pcie_driver);\n+\n+MODULE_DESCRIPTION(\"UltraRISC DP1000 DWC PCIe host controller\");\n+MODULE_LICENSE(\"GPL\");\n","prefixes":["v4","3/3"]}