{"id":2228552,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2228552/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260427-ultrarisc-pcie-v4-2-98935f6cdfb5@ultrarisc.com/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/1.2/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260427-ultrarisc-pcie-v4-2-98935f6cdfb5@ultrarisc.com>","list_archive_url":null,"date":"2026-04-27T01:32:11","name":"[v4,2/3] dt-bindings: PCI: Add UltraRISC DP1000 PCIe controller","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"648e1e8123c7584e535a065a7ceab5ac0bc64a57","submitter":{"id":92886,"url":"http://patchwork.ozlabs.org/api/1.2/people/92886/?format=json","name":"Jia Wang","email":"wangjia@ultrarisc.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260427-ultrarisc-pcie-v4-2-98935f6cdfb5@ultrarisc.com/mbox/","series":[{"id":501558,"url":"http://patchwork.ozlabs.org/api/1.2/series/501558/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/list/?series=501558","date":"2026-04-27T01:32:09","name":"riscv: Add PCIe support for UltraRISC DP1000 SoC","version":4,"mbox":"http://patchwork.ozlabs.org/series/501558/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2228552/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2228552/checks/","tags":{},"related":[],"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=ultrarisc.com header.i=@ultrarisc.com\n header.a=rsa-sha256 header.s=dkim header.b=AFal1g22;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c15:e001:75::12fc:5321; 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a=rsa-sha256; c=relaxed/relaxed;\n\td=ultrarisc.com; s=dkim; h=Received:From:Date:Subject:\n\tMIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:\n\tReferences:In-Reply-To:To:Cc; bh=HYT/JtcTeb4xRDUsI9fYBdNKr0Iy0dm\n\tMBfAidPI4MF0=; b=AFal1g22bTU1RB0ZyPdZxZh1Gr5dgbxDw1U3ujsC7Ba4e19\n\tg/Co9uTO78COGOtBGNerxdqBcZbJvRIVPeIzWswL3Yzx1q45rElfpcB/Vx40MiHJ\n\t7gu9G9fbs7JSYHSlgxvu697lLEpkMAWy5VAM6rK79H8BElhFvnWGnyCW5CeU=","From":"Jia Wang ","Date":"Mon, 27 Apr 2026 09:32:11 +0800","Subject":"[PATCH v4 2/3] dt-bindings: PCI: Add UltraRISC DP1000 PCIe\n controller","Precedence":"bulk","X-Mailing-List":"linux-pci@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"7bit","Message-Id":"<20260427-ultrarisc-pcie-v4-2-98935f6cdfb5@ultrarisc.com>","References":"<20260427-ultrarisc-pcie-v4-0-98935f6cdfb5@ultrarisc.com>","In-Reply-To":"<20260427-ultrarisc-pcie-v4-0-98935f6cdfb5@ultrarisc.com>","To":"Paul Walmsley , Palmer Dabbelt ,\n Albert Ou , Alexandre Ghiti ,\n Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?=\n\t=?utf-8?q?=C5=84ski?= ,\n Manivannan Sadhasivam , Rob Herring ,\n Bjorn Helgaas , Jingoo Han ,\n Xincheng Zhang ,\n Krzysztof Kozlowski ,\n Conor Dooley ","Cc":"linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,\n linux-pci@vger.kernel.org, devicetree@vger.kernel.org,\n Jia Wang ,\n Krzysztof Kozlowski ","X-Mailer":"b4 0.15-dev","X-Developer-Signature":"v=1; a=ed25519-sha256; t=1777253539; l=3982;\n i=wangjia@ultrarisc.com; s=20260309; h=from:subject:message-id;\n bh=X2bzlR0Ihg946bcqWPf1jyyPRrQHRRPJWRN220hfPCo=;\n b=lshqQvLyVCLepawcXw2Cbbkx0v3nUFfXgwvfeqxhZwaD45Ew/JmEnP0f8MOvq2H/eUjgWrpFx\n rV+O9xzlmGQDmAr1ex4NAvl1/AGEZK4jTxc0cv1tFgVvXCt79CpmbSP","X-Developer-Key":"i=wangjia@ultrarisc.com; a=ed25519;\n pk=XvYkrelqJIIzobY7j+nIg8rsfv5kzaOzuc1UPhd087U=","X-CM-TRANSID":"AQAAfwA3cULPvO5ps_0CAA--.1758S4","X-Coremail-Antispam":"1UD129KBjvJXoWxGryDXryUGw15XrW5WFW8Xrb_yoW5Kw17pF\n\tWUCa4kuF4xtr13uw4fK3W0kF15XF4vkF9YywnFgw1UtFZYgw1jqrsIkw13G3W5Gr4UXry2\n\tgFn0kr17Kw4UAw7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2\n\t9KBjDU0xBIdaVrnUUvcSsGvfC2KfnxnUUI43ZEXa7xR_UUUUUUUUU==","X-CM-SenderInfo":"pzdqwylld63zxwud2x1vfou0bp/1tbiAQAKEWnti78ABwAAst"},"content":"Add UltraRISC DP1000 SoC PCIe controller devicetree bindings.\n\nSigned-off-by: Jia Wang \nReviewed-by: Krzysztof Kozlowski \n---\n .../bindings/pci/ultrarisc,dp1000-pcie.yaml | 93 ++++++++++++++++++++++\n MAINTAINERS | 7 ++\n 2 files changed, 100 insertions(+)","diff":"diff --git a/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml\nnew file mode 100644\nindex 000000000000..512b935bf5d1\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml\n@@ -0,0 +1,93 @@\n+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/pci/ultrarisc,dp1000-pcie.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: UltraRISC DP1000 PCIe Host Controller\n+\n+description:\n+ UltraRISC DP1000 SoC PCIe host controller is based on the DesignWare PCIe IP.\n+\n+maintainers:\n+ - Xincheng Zhang \n+ - Jia Wang \n+\n+allOf:\n+ - $ref: /schemas/pci/snps,dw-pcie.yaml#\n+\n+properties:\n+ compatible:\n+ const: ultrarisc,dp1000-pcie\n+\n+ reg:\n+ items:\n+ - description: Data Bus Interface (DBI) registers.\n+ - description: PCIe configuration space region.\n+\n+ reg-names:\n+ items:\n+ - const: dbi\n+ - const: config\n+\n+ num-lanes:\n+ $ref: /schemas/types.yaml#/definitions/uint32\n+ enum: [4, 16]\n+ description: Number of lanes to use.\n+\n+ interrupts:\n+ items:\n+ - description: MSI interrupt\n+ - description: Legacy INTA interrupt\n+ - description: Legacy INTB interrupt\n+ - description: Legacy INTC interrupt\n+ - description: Legacy INTD interrupt\n+\n+ interrupt-names:\n+ items:\n+ - const: msi\n+ - const: inta\n+ - const: intb\n+ - const: intc\n+ - const: intd\n+\n+required:\n+ - compatible\n+ - reg\n+ - reg-names\n+ - interrupts\n+ - interrupt-names\n+\n+unevaluatedProperties: false\n+\n+examples:\n+ - |\n+ soc {\n+ #address-cells = <2>;\n+ #size-cells = <2>;\n+\n+ pcie@21000000 {\n+ compatible = \"ultrarisc,dp1000-pcie\";\n+ reg = <0x0 0x21000000 0x0 0x01000000>,\n+ <0x0 0x4fff0000 0x0 0x00010000>;\n+ reg-names = \"dbi\", \"config\";\n+ ranges = <0x81000000 0x0 0x4fbf0000 0x0 0x4fbf0000 0x0 0x00400000>,\n+ <0x82000000 0x0 0x40000000 0x0 0x40000000 0x0 0x0fbf0000>,\n+ <0xc3000000 0x40 0x00000000 0x40 0x00000000 0xd 0x00000000>;\n+ #address-cells = <3>;\n+ #size-cells = <2>;\n+ #interrupt-cells = <1>;\n+ device_type = \"pci\";\n+ dma-coherent;\n+ bus-range = <0x0 0xff>;\n+ num-lanes = <16>;\n+ interrupt-parent = <&plic>;\n+ interrupts = <43>, <44>, <45>, <46>, <47>;\n+ interrupt-names = \"msi\", \"inta\", \"intb\", \"intc\", \"intd\";\n+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;\n+ interrupt-map = <0x0 0x0 0x0 0x1 &plic 44>,\n+ <0x0 0x0 0x0 0x2 &plic 45>,\n+ <0x0 0x0 0x0 0x3 &plic 46>,\n+ <0x0 0x0 0x0 0x4 &plic 47>;\n+ };\n+ };\ndiff --git a/MAINTAINERS b/MAINTAINERS\nindex d238590a31f2..818685933541 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -20583,6 +20583,13 @@ S:\tMaintained\n F:\tDocumentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml\n F:\tdrivers/pci/controller/plda/pcie-starfive.c\n \n+PCIE DRIVER FOR ULTRARISC DP1000\n+M:\tXincheng Zhang \n+M:\tJia Wang \n+L:\tlinux-pci@vger.kernel.org\n+S:\tMaintained\n+F:\tDocumentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml\n+\n PCIE ENDPOINT DRIVER FOR QUALCOMM\n M:\tManivannan Sadhasivam \n L:\tlinux-pci@vger.kernel.org\n","prefixes":["v4","2/3"]}