{"id":2227866,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2227866/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260424201842.176953-2-junjie.cao@intel.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260424201842.176953-2-junjie.cao@intel.com>","list_archive_url":null,"date":"2026-04-24T20:18:41","name":"[v2,1/2] intel_iommu: widen impl.min_access_size to 8 to fix MMIO abort","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"3a3ad539419684db9c334513143c6370bf4e28e6","submitter":{"id":91537,"url":"http://patchwork.ozlabs.org/api/1.2/people/91537/?format=json","name":"Junjie Cao","email":"junjie.cao@intel.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260424201842.176953-2-junjie.cao@intel.com/mbox/","series":[{"id":501352,"url":"http://patchwork.ozlabs.org/api/1.2/series/501352/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501352","date":"2026-04-24T20:18:40","name":"intel_iommu: fix guest-triggerable assert in MMIO handlers","version":2,"mbox":"http://patchwork.ozlabs.org/series/501352/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2227866/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2227866/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=WNz6ooTH;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Fri, 24 Apr 2026 08:16:05 -0400","from fmviesa005.fm.intel.com ([10.60.135.145])\n by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 24 Apr 2026 05:16:01 -0700","from junjie-optiplex-micro-plus-7010.bj.intel.com ([10.238.152.98])\n by fmviesa005-auth.fm.intel.com with\n ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2026 05:15:59 -0700"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1777032963; x=1808568963;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=I2CalveJmINak9hL6z6R/gQ3HHeQaE7OTNeBaf8Pqdg=;\n b=WNz6ooTHhc4staxJTMtPxjBXyHypzJEolarGlg2/iWrswNcbhghdC8L0\n xGyf2QOfuriT7fwgUggHvsouFAjVU5PWoPw8a9eD0ryueY5W3U/qNDk2p\n rxGbAhDHKfujqRdVxexpuza9EuWKGFGAzt6M5o2LyPx4wqe07wOKvF84z\n FC4/jFnlwvOvOu5KwSiW6x+U8hDfVQSxk2Ju95usmdb7Em5HLdy9hHxMP\n souBdEawQbHUA4D4wZ6uwBGhbC8+T946+aR70Jcg0FRGjZRTKhEJR7Gbx\n tcTRH7cjdMNM0wDFe6SQ3TpqmAFFTn/EEyoFNNcOABQF4dI7i5Pq18si4 w==;","X-CSE-ConnectionGUID":["ymxTPIy3R2u5yhWU/z6bvQ==","bdy9EzsnTOOaBwPgITz7uw=="],"X-CSE-MsgGUID":["ZoWdkWlDQYmg0XZSD+EzWQ==","V8fKUnEjQAmvP3Nnrd4CFg=="],"X-IronPort-AV":["E=McAfee;i=\"6800,10657,11765\"; a=\"78029979\"","E=Sophos;i=\"6.23,196,1770624000\"; d=\"scan'208\";a=\"78029979\"","E=Sophos;i=\"6.23,196,1770624000\"; d=\"scan'208\";a=\"237935768\""],"X-ExtLoop1":"1","From":"Junjie Cao ","To":"qemu-devel@nongnu.org","Cc":"junjie.cao@intel.com, mst@redhat.com, jasowang@redhat.com,\n yi.l.liu@intel.com, clement.mathieu--drif@bull.com, philmd@linaro.org,\n zhenzhong.duan@intel.com","Subject":"[PATCH v2 1/2] intel_iommu: widen impl.min_access_size to 8 to fix\n MMIO abort","Date":"Sat, 25 Apr 2026 04:18:41 +0800","Message-ID":"<20260424201842.176953-2-junjie.cao@intel.com>","X-Mailer":"git-send-email 2.43.0","In-Reply-To":"<20260424201842.176953-1-junjie.cao@intel.com>","References":"<20260424201842.176953-1-junjie.cao@intel.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=UTF-8","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=198.175.65.18;\n envelope-from=junjie.cao@intel.com;\n helo=mgamail.intel.com","X-Spam_score_int":"-24","X-Spam_score":"-2.5","X-Spam_bar":"--","X-Spam_report":"(-2.5 / 5.0 requ) BAYES_00=-1.9, DATE_IN_FUTURE_06_12=1.947,\n DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1,\n DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Raise .impl.min_access_size from 4 to 8 in vtd_mem_ops so the memory\nsubsystem always widens guest accesses to 8 bytes before calling the\nhandler. This eliminates all 25 assert(size == 4) sites that crashed\nQEMU on an 8-byte access to a 32-bit-only register.\n\nWith size always 8, the if/else branches for 64-bit register pairs\ncollapse. A zero-extended 4-byte write to the low half is safe:\nwmask protects read-only upper bits, and trigger functions re-read\nthe register file and guard on their action bits.\n\nThe entry bounds check is relaxed to `addr >= DMAR_REG_SIZE` since\nthe widened size no longer reflects the guest access width; the\nframework guarantees addr stays within the MemoryRegion. Default\nbranches fall back to vtd_get/set_long() when addr + 8 would exceed\nthe register file.\n\nSuggested-by: Philippe Mathieu-Daudé \nSigned-off-by: Junjie Cao \n---\n hw/i386/intel_iommu.c | 121 ++++++++----------------------------------\n 1 file changed, 23 insertions(+), 98 deletions(-)","diff":"diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c\nindex f395fa248c..4b25907778 100644\n--- a/hw/i386/intel_iommu.c\n+++ b/hw/i386/intel_iommu.c\n@@ -3697,7 +3697,7 @@ static uint64_t vtd_mem_read(void *opaque, hwaddr addr, unsigned size)\n \n trace_vtd_reg_read(addr, size);\n \n- if (addr + size > DMAR_REG_SIZE) {\n+ if (addr >= DMAR_REG_SIZE) {\n error_report_once(\"%s: MMIO over range: addr=0x%\" PRIx64\n \" size=0x%x\", __func__, addr, size);\n return (uint64_t)-1;\n@@ -3707,13 +3707,9 @@ static uint64_t vtd_mem_read(void *opaque, hwaddr addr, unsigned size)\n /* Root Table Address Register, 64-bit */\n case DMAR_RTADDR_REG:\n val = vtd_get_quad_raw(s, DMAR_RTADDR_REG);\n- if (size == 4) {\n- val = val & ((1ULL << 32) - 1);\n- }\n break;\n \n case DMAR_RTADDR_REG_HI:\n- assert(size == 4);\n val = vtd_get_quad_raw(s, DMAR_RTADDR_REG) >> 32;\n break;\n \n@@ -3722,26 +3718,21 @@ static uint64_t vtd_mem_read(void *opaque, hwaddr addr, unsigned size)\n val = s->iq |\n (vtd_get_quad(s, DMAR_IQA_REG) &\n (VTD_IQA_QS | VTD_IQA_DW_MASK));\n- if (size == 4) {\n- val = val & ((1ULL << 32) - 1);\n- }\n break;\n \n case DMAR_IQA_REG_HI:\n- assert(size == 4);\n val = s->iq >> 32;\n break;\n \n case DMAR_PEUADDR_REG:\n- assert(size == 4);\n val = vtd_get_long_raw(s, DMAR_PEUADDR_REG);\n break;\n \n default:\n- if (size == 4) {\n- val = vtd_get_long(s, addr);\n- } else {\n+ if (addr + 8 <= DMAR_REG_SIZE) {\n val = vtd_get_quad(s, addr);\n+ } else {\n+ val = vtd_get_long(s, addr);\n }\n }\n \n@@ -3755,7 +3746,7 @@ static void vtd_mem_write(void *opaque, hwaddr addr,\n \n trace_vtd_reg_write(addr, size, val);\n \n- if (addr + size > DMAR_REG_SIZE) {\n+ if (addr >= DMAR_REG_SIZE) {\n error_report_once(\"%s: MMIO over range: addr=0x%\" PRIx64\n \" size=0x%x\", __func__, addr, size);\n return;\n@@ -3770,238 +3761,172 @@ static void vtd_mem_write(void *opaque, hwaddr addr,\n \n /* Context Command Register, 64-bit */\n case DMAR_CCMD_REG:\n- if (size == 4) {\n- vtd_set_long(s, addr, val);\n- } else {\n- vtd_set_quad(s, addr, val);\n- vtd_handle_ccmd_write(s);\n- }\n+ vtd_set_quad(s, addr, val);\n+ vtd_handle_ccmd_write(s);\n break;\n \n case DMAR_CCMD_REG_HI:\n- assert(size == 4);\n vtd_set_long(s, addr, val);\n vtd_handle_ccmd_write(s);\n break;\n \n /* IOTLB Invalidation Register, 64-bit */\n case DMAR_IOTLB_REG:\n- if (size == 4) {\n- vtd_set_long(s, addr, val);\n- } else {\n- vtd_set_quad(s, addr, val);\n- vtd_handle_iotlb_write(s);\n- }\n+ vtd_set_quad(s, addr, val);\n+ vtd_handle_iotlb_write(s);\n break;\n \n case DMAR_IOTLB_REG_HI:\n- assert(size == 4);\n vtd_set_long(s, addr, val);\n vtd_handle_iotlb_write(s);\n break;\n \n case DMAR_PEUADDR_REG:\n- assert(size == 4);\n vtd_set_long(s, addr, val);\n break;\n \n /* Invalidate Address Register, 64-bit */\n case DMAR_IVA_REG:\n- if (size == 4) {\n- vtd_set_long(s, addr, val);\n- } else {\n- vtd_set_quad(s, addr, val);\n- }\n+ vtd_set_quad(s, addr, val);\n break;\n \n case DMAR_IVA_REG_HI:\n- assert(size == 4);\n vtd_set_long(s, addr, val);\n break;\n \n /* Fault Status Register, 32-bit */\n case DMAR_FSTS_REG:\n- assert(size == 4);\n vtd_set_long(s, addr, val);\n vtd_handle_fsts_write(s);\n break;\n \n /* Fault Event Control Register, 32-bit */\n case DMAR_FECTL_REG:\n- assert(size == 4);\n vtd_set_long(s, addr, val);\n vtd_handle_fectl_write(s);\n break;\n \n /* Fault Event Data Register, 32-bit */\n case DMAR_FEDATA_REG:\n- assert(size == 4);\n vtd_set_long(s, addr, val);\n break;\n \n /* Fault Event Address Register, 32-bit */\n case DMAR_FEADDR_REG:\n- if (size == 4) {\n- vtd_set_long(s, addr, val);\n- } else {\n- /*\n- * While the register is 32-bit only, some guests (Xen...) write to\n- * it with 64-bit.\n- */\n- vtd_set_quad(s, addr, val);\n- }\n+ vtd_set_quad(s, addr, val);\n break;\n \n /* Fault Event Upper Address Register, 32-bit */\n case DMAR_FEUADDR_REG:\n- assert(size == 4);\n vtd_set_long(s, addr, val);\n break;\n \n /* Protected Memory Enable Register, 32-bit */\n case DMAR_PMEN_REG:\n- assert(size == 4);\n vtd_set_long(s, addr, val);\n break;\n \n /* Root Table Address Register, 64-bit */\n case DMAR_RTADDR_REG:\n- if (size == 4) {\n- vtd_set_long(s, addr, val);\n- } else {\n- vtd_set_quad(s, addr, val);\n- }\n+ vtd_set_quad(s, addr, val);\n break;\n \n case DMAR_RTADDR_REG_HI:\n- assert(size == 4);\n vtd_set_long(s, addr, val);\n break;\n \n /* Invalidation Queue Tail Register, 64-bit */\n case DMAR_IQT_REG:\n- if (size == 4) {\n- vtd_set_long(s, addr, val);\n- } else {\n- vtd_set_quad(s, addr, val);\n- }\n+ vtd_set_quad(s, addr, val);\n vtd_handle_iqt_write(s);\n break;\n \n case DMAR_IQT_REG_HI:\n- assert(size == 4);\n vtd_set_long(s, addr, val);\n /* 19:63 of IQT_REG is RsvdZ, do nothing here */\n break;\n \n /* Invalidation Queue Address Register, 64-bit */\n case DMAR_IQA_REG:\n- if (size == 4) {\n- vtd_set_long(s, addr, val);\n- } else {\n- vtd_set_quad(s, addr, val);\n- }\n+ vtd_set_quad(s, addr, val);\n vtd_update_iq_dw(s);\n break;\n \n case DMAR_IQA_REG_HI:\n- assert(size == 4);\n vtd_set_long(s, addr, val);\n break;\n \n /* Invalidation Completion Status Register, 32-bit */\n case DMAR_ICS_REG:\n- assert(size == 4);\n vtd_set_long(s, addr, val);\n vtd_handle_ics_write(s);\n break;\n \n /* Invalidation Event Control Register, 32-bit */\n case DMAR_IECTL_REG:\n- assert(size == 4);\n vtd_set_long(s, addr, val);\n vtd_handle_iectl_write(s);\n break;\n \n /* Invalidation Event Data Register, 32-bit */\n case DMAR_IEDATA_REG:\n- assert(size == 4);\n vtd_set_long(s, addr, val);\n break;\n \n /* Invalidation Event Address Register, 32-bit */\n case DMAR_IEADDR_REG:\n- assert(size == 4);\n vtd_set_long(s, addr, val);\n break;\n \n /* Invalidation Event Upper Address Register, 32-bit */\n case DMAR_IEUADDR_REG:\n- assert(size == 4);\n vtd_set_long(s, addr, val);\n break;\n \n /* Fault Recording Registers, 128-bit */\n case DMAR_FRCD_REG_0_0:\n- if (size == 4) {\n- vtd_set_long(s, addr, val);\n- } else {\n- vtd_set_quad(s, addr, val);\n- }\n+ vtd_set_quad(s, addr, val);\n break;\n \n case DMAR_FRCD_REG_0_1:\n- assert(size == 4);\n vtd_set_long(s, addr, val);\n break;\n \n case DMAR_FRCD_REG_0_2:\n- if (size == 4) {\n- vtd_set_long(s, addr, val);\n- } else {\n- vtd_set_quad(s, addr, val);\n- /* May clear bit 127 (Fault), update PPF */\n- vtd_update_fsts_ppf(s);\n- }\n+ vtd_set_quad(s, addr, val);\n+ /* May clear bit 127 (Fault), update PPF */\n+ vtd_update_fsts_ppf(s);\n break;\n \n case DMAR_FRCD_REG_0_3:\n- assert(size == 4);\n vtd_set_long(s, addr, val);\n /* May clear bit 127 (Fault), update PPF */\n vtd_update_fsts_ppf(s);\n break;\n \n case DMAR_IRTA_REG:\n- if (size == 4) {\n- vtd_set_long(s, addr, val);\n- } else {\n- vtd_set_quad(s, addr, val);\n- }\n+ vtd_set_quad(s, addr, val);\n break;\n \n case DMAR_IRTA_REG_HI:\n- assert(size == 4);\n vtd_set_long(s, addr, val);\n break;\n \n case DMAR_PRS_REG:\n- assert(size == 4);\n vtd_set_long(s, addr, val);\n vtd_handle_prs_write(s);\n break;\n \n case DMAR_PECTL_REG:\n- assert(size == 4);\n vtd_set_long(s, addr, val);\n vtd_handle_pectl_write(s);\n break;\n \n default:\n- if (size == 4) {\n- vtd_set_long(s, addr, val);\n- } else {\n+ if (addr + 8 <= DMAR_REG_SIZE) {\n vtd_set_quad(s, addr, val);\n+ } else {\n+ vtd_set_long(s, addr, val);\n }\n }\n }\n@@ -4184,7 +4109,7 @@ static const MemoryRegionOps vtd_mem_ops = {\n .write = vtd_mem_write,\n .endianness = DEVICE_LITTLE_ENDIAN,\n .impl = {\n- .min_access_size = 4,\n+ .min_access_size = 8,\n .max_access_size = 8,\n },\n .valid = {\n","prefixes":["v2","1/2"]}