{"id":2226266,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2226266/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/patch/bmm.hhubd62wbc.gcc.gcc-TEST.pinskia.20.1.8@forge-stage.sourceware.org/","project":{"id":17,"url":"http://patchwork.ozlabs.org/api/1.2/projects/17/?format=json","name":"GNU Compiler Collection","link_name":"gcc","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"","list_archive_url":null,"date":"2026-04-22T10:29:53","name":"[v1,08/11] Fix","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"310aec32b80928cf16dff21eebacf0b04cb924fd","submitter":{"id":93219,"url":"http://patchwork.ozlabs.org/api/1.2/people/93219/?format=json","name":"Andrew Pinski via Sourceware Forge","email":"forge-bot+pinskia@forge-stage.sourceware.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/gcc/patch/bmm.hhubd62wbc.gcc.gcc-TEST.pinskia.20.1.8@forge-stage.sourceware.org/mbox/","series":[{"id":500972,"url":"http://patchwork.ozlabs.org/api/1.2/series/500972/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/list/?series=500972","date":"2026-04-22T10:29:49","name":"WIP: v2hiv4qi","version":1,"mbox":"http://patchwork.ozlabs.org/series/500972/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2226266/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2226266/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","gcc-patches@gcc.gnu.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","gcc-patches@gcc.gnu.org"],"Authentication-Results":["legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; 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server2.sourceware.org","From":"Andrew Pinski via Sourceware Forge\n ","Date":"Wed, 22 Apr 2026 10:29:53 +0000","Subject":"[PATCH v1 08/11] Fix","To":"gcc-patches mailing list ","Message-ID":"\n ","X-Mailer":"batrachomyomachia","X-Pull-Request-Organization":"gcc","X-Pull-Request-Repository":"gcc-TEST","X-Pull-Request":"https://forge.sourceware.org/gcc/gcc-TEST/pulls/20","References":"\n ","In-Reply-To":"\n ","X-Patch-URL":"\n https://forge.sourceware.org/pinskia/gcc-TEST/commit/e0fcf0c81d4ae9d6c9ce2c229b9a3a4d2dc789d3","X-BeenThere":"gcc-patches@gcc.gnu.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Gcc-patches mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Reply-To":"gcc-patches mailing list ,\n pinskia@gcc.gnu.org","Errors-To":"gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org"},"content":"From: Andrew Pinski \n\nSigned-off-by: Andrew Pinski \n---\n gcc/config/aarch64/aarch64-simd.md | 4 ++--\n gcc/config/aarch64/aarch64-sve.md | 8 ++++----\n gcc/config/aarch64/iterators.md | 10 +++++++---\n 3 files changed, 13 insertions(+), 9 deletions(-)","diff":"diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md\nindex 1cee004664ca..22763d683b61 100644\n--- a/gcc/config/aarch64/aarch64-simd.md\n+++ b/gcc/config/aarch64/aarch64-simd.md\n@@ -323,7 +323,7 @@\n \n (define_insn \"iorn3\"\n [(set (match_operand:VDQS_I 0 \"register_operand\" \"=w\")\n- (ior:VDQ_I (not:VDQS_I (match_operand:VDQ_I 2 \"register_operand\" \"w\"))\n+ (ior:VDQS_I (not:VDQS_I (match_operand:VDQS_I 2 \"register_operand\" \"w\"))\n \t\t(match_operand:VDQS_I 1 \"register_operand\" \"w\")))]\n \"TARGET_SIMD\"\n \"orn\\t%0., %1., %2.\"\n@@ -332,7 +332,7 @@\n \n (define_insn \"andn3\"\n [(set (match_operand:VDQS_I 0 \"register_operand\" \"=w\")\n- (and:VDQ_I (not:VDQS_I (match_operand:VDQ_I 2 \"register_operand\" \"w\"))\n+ (and:VDQS_I (not:VDQS_I (match_operand:VDQS_I 2 \"register_operand\" \"w\"))\n \t\t(match_operand:VDQS_I 1 \"register_operand\" \"w\")))]\n \"TARGET_SIMD\"\n \"bic\\t%0., %1., %2.\"\ndiff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md\nindex 06bd3e4bb2c0..d2afb59e40ca 100644\n--- a/gcc/config/aarch64/aarch64-sve.md\n+++ b/gcc/config/aarch64/aarch64-sve.md\n@@ -3121,11 +3121,11 @@\n \n ;; Integer unary arithmetic predicated with a PTRUE.\n (define_insn \"@aarch64_pred_\"\n- [(set (match_operand:SVE_VDQ_I 0 \"register_operand\")\n-\t(unspec:SVE_VDQ_I\n+ [(set (match_operand:SVE_VDQS_I 0 \"register_operand\")\n+\t(unspec:SVE_VDQS_I\n \t [(match_operand: 1 \"register_operand\")\n-\t (SVE_INT_UNARY:SVE_VDQ_I\n-\t (match_operand:SVE_VDQ_I 2 \"register_operand\"))]\n+\t (SVE_INT_UNARY:SVE_VDQS_I\n+\t (match_operand:SVE_VDQS_I 2 \"register_operand\"))]\n \t UNSPEC_PRED_X))]\n \"TARGET_SVE\"\n {@ [ cons: =0 , 1 , 2 ; attrs: movprfx ]\ndiff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md\nindex c042da62a870..5e8d42ca4f1d 100644\n--- a/gcc/config/aarch64/iterators.md\n+++ b/gcc/config/aarch64/iterators.md\n@@ -87,7 +87,7 @@\n (define_mode_iterator VDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI])\n \n ;; Integer Advanced SIMD modes plus 32bit modes\n-(define_mode_iterator VDQS_I [V4QI V2HI V8QI V16QI V4HI V8HI V2SI V4SI V2DI])\n+(define_mode_iterator VDQS_I [V4QI V2HI VDQ_I])\n \n ;; Advanced SIMD and scalar, 64 & 128-bit container, all integer modes.\n (define_mode_iterator VSDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI QI HI SI DI])\n@@ -97,7 +97,7 @@\n (define_mode_iterator VSDQ_I_DI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI DI])\n \n ;; Same as above plus the 32bit modes\n-(define_mode_iterator VSDQS_I_DI [V4QI V2HI V8QI V16QI V4HI V8HI V2SI V4SI V2DI DI])\n+(define_mode_iterator VSDQS_I_DI [V4QI V2HI VSDQ_I_DI])\n \n ;; Double vector modes.\n (define_mode_iterator VD [V8QI V4HI V4HF V2SI V2SF V4BF])\n@@ -127,7 +127,7 @@\n (define_mode_iterator VDQ_BHSI [V8QI V16QI V4HI V8HI V2SI V4SI])\n \n ;; 128, 64, and 32-bit container; 8, 16, 32-bit vector integer modes\n-(define_mode_iterator VDQS_BHSI [V4QI V2HI V8QI V16QI V4HI V8HI V2SI V4SI])\n+(define_mode_iterator VDQS_BHSI [V4QI V2HI VDQ_BHSI])\n \n ;; Quad vector modes.\n (define_mode_iterator VQ [V16QI V8HI V4SI V2DI V8HF V4SF V2DF V8BF])\n@@ -606,6 +606,9 @@\n ;; All SVE and Advanced SIMD integer vector modes.\n (define_mode_iterator SVE_VDQ_I [SVE_I VDQ_I V1DI])\n \n+;; All SVE and Advanced SIMD integer vector modes.\n+(define_mode_iterator SVE_VDQS_I [SVE_I VDQS_I])\n+\n ;; SVE integer vector modes whose elements are 16 bits or wider.\n (define_mode_iterator SVE_HSDI [VNx8HI VNx4HI VNx2HI\n \t\t\t\tVNx4SI VNx2SI\n@@ -2361,6 +2364,7 @@\n \t\t\t (VNx32BF \"VNx8BI\")\n \t\t\t (VNx16SI \"VNx4BI\") (VNx16SF \"VNx4BI\")\n \t\t\t (VNx8DI \"VNx2BI\") (VNx8DF \"VNx2BI\")\n+\t\t\t (V4QI \"VNx4BI\") (V2HI \"VNx2BI\")\n \t\t\t (V8QI \"VNx8BI\") (V16QI \"VNx16BI\")\n \t\t\t (V4HI \"VNx4BI\") (V8HI \"VNx8BI\") (V2SI \"VNx2BI\")\n \t\t\t (V4SI \"VNx4BI\") (V2DI \"VNx2BI\") (V1DI \"VNx2BI\")])\n","prefixes":["v1","08/11"]}