{"id":2226163,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2226163/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260422101043.1234229-30-alex.bennee@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260422101043.1234229-30-alex.bennee@linaro.org>","list_archive_url":null,"date":"2026-04-22T10:10:40","name":"[v2,29/31] target/arm: implement global monitor events","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"de78f4173d1f4fd933fe2c213fa0cbbe9d35ca43","submitter":{"id":39532,"url":"http://patchwork.ozlabs.org/api/1.2/people/39532/?format=json","name":"Alex Bennée","email":"alex.bennee@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260422101043.1234229-30-alex.bennee@linaro.org/mbox/","series":[{"id":500957,"url":"http://patchwork.ozlabs.org/api/1.2/series/500957/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500957","date":"2026-04-22T10:10:11","name":"target/arm: fully model WFxT instructions for A-profile","version":2,"mbox":"http://patchwork.ozlabs.org/series/500957/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2226163/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2226163/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=fArmz0Pb;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2a00:1450:4864:20::329;\n envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x329.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Moving from Exclusive to Open Access should generate event stream\nevents. Technically a non-exclusive store to any address range covered\nby the global monitor should also trigger such an event but we can\nonly detect that after the event by seeing if memory doesn't match\ncpu_exclusive_val when processing the eventual store exclusive.\n\nThe CLREX instruction has the same effect as do other operations\nclearing the exclusive state (such as eret).\n\nWe special case STLR/STL (Store Release) instructions to generate\nevents because their use is a suggested pattern for clearing locks\nthat might be sleeping. We only trigger the event if we detect an\nexclusive instruction is running.\n\nSigned-off-by: Alex Bennée \n\n---\nv2\n - add gen_global_event_reg() and use that\n - add handling for STL/STLR\n---\n target/arm/internals.h | 1 +\n target/arm/tcg/translate.h | 14 ++++++++++++++\n target/arm/tcg/translate-a64.c | 23 +++++++++++++++++++++++\n target/arm/tcg/translate.c | 20 ++++++++++++++++++++\n 4 files changed, 58 insertions(+)","diff":"diff --git a/target/arm/internals.h b/target/arm/internals.h\nindex 089f679ac0a..7045b4a56bd 100644\n--- a/target/arm/internals.h\n+++ b/target/arm/internals.h\n@@ -709,6 +709,7 @@ static inline void arm_broadcast_event(void)\n static inline void arm_clear_exclusive(CPUARMState *env)\n {\n env->exclusive_addr = -1;\n+ arm_broadcast_event();\n }\n \n /**\ndiff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h\nindex 9bf2701a56b..01053060af4 100644\n--- a/target/arm/tcg/translate.h\n+++ b/target/arm/tcg/translate.h\n@@ -882,6 +882,20 @@ static inline void gen_event_reg(void)\n #endif\n }\n \n+/*\n+ * Some events affect all PEs in the same shareability domain. In\n+ * practice as we currently model SMP systems as single SoC devices so\n+ * we signal them all.\n+ */\n+static inline void gen_global_event_reg(void)\n+{\n+#ifndef CONFIG_USER_ONLY\n+ /* re-use the SEV helper */\n+ gen_helper_sev(tcg_env);\n+#endif\n+}\n+\n+\n /*\n * Helpers for implementing sets of trans_* functions.\n * Defer the implementation of NAME to FUNC, with optional extra arguments.\ndiff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c\nindex f30df5dbfed..a1b0cc9508e 100644\n--- a/target/arm/tcg/translate-a64.c\n+++ b/target/arm/tcg/translate-a64.c\n@@ -2253,6 +2253,7 @@ static bool trans_CHKFEAT(DisasContext *s, arg_CHKFEAT *a)\n static bool trans_CLREX(DisasContext *s, arg_CLREX *a)\n {\n tcg_gen_movi_i64(cpu_exclusive_addr, -1);\n+ gen_global_event_reg();\n return true;\n }\n \n@@ -3407,6 +3408,14 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,\n tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, cpu_exclusive_val);\n }\n tcg_gen_mov_i64(cpu_reg(s, rd), tmp);\n+\n+ /*\n+ * On a successful StoreExcl the global monitor transitions from\n+ * Exclusive to Open Access and at that point generate an Event\n+ * for PEs in the same memory sharing domain.\n+ */\n+ gen_global_event_reg();\n+\n tcg_gen_br(done_label);\n \n gen_set_label(fail_label);\n@@ -3544,6 +3553,7 @@ static bool trans_STLR(DisasContext *s, arg_stlr *a)\n TCGv_i64 clean_addr;\n MemOp memop;\n bool iss_sf = ldst_iss_sf(a->sz, false, false);\n+ TCGLabel *skip_monitor_event = gen_new_label();\n \n /*\n * StoreLORelease is the same as Store-Release for QEMU, but\n@@ -3562,6 +3572,19 @@ static bool trans_STLR(DisasContext *s, arg_stlr *a)\n true, a->rn != 31, memop);\n do_gpr_st(s, cpu_reg(s, a->rt), clean_addr, memop, true, a->rt,\n iss_sf, a->lasr);\n+\n+ /*\n+ * We don't fully model the global monitor as it would be very\n+ * expensive for every memory access. However in the Arm ARM \"Use\n+ * of Wait for Event (WFE) and Send Event (SEV) with lock\" it does\n+ * give the example of using STLR to clear a lock. So if a lock is\n+ * active trigger the global event register so we don't deadlock\n+ * while sleeping.\n+ */\n+ tcg_gen_brcondi_i64(TCG_COND_EQ, cpu_exclusive_addr, -1, skip_monitor_event);\n+ gen_global_event_reg();\n+ gen_set_label(skip_monitor_event);\n+\n return true;\n }\n \ndiff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c\nindex 59925151fc3..18d64620e40 100644\n--- a/target/arm/tcg/translate.c\n+++ b/target/arm/tcg/translate.c\n@@ -2116,6 +2116,12 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,\n tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t2);\n }\n tcg_gen_mov_i32(cpu_R[rd], t0);\n+ /*\n+ * On a successful StoreExcl the global monitor transitions from\n+ * Exclusive to Open Access and at that point generate an Event\n+ * for PEs in the same memory sharing domain.\n+ */\n+ gen_global_event_reg();\n tcg_gen_br(done_label);\n \n gen_set_label(fail_label);\n@@ -4218,6 +4224,7 @@ static bool trans_STLEXH(DisasContext *s, arg_STREX *a)\n static bool op_stl(DisasContext *s, arg_STL *a, MemOp mop)\n {\n TCGv_i32 addr, tmp;\n+ TCGLabel *skip_monitor_event;\n \n if (!ENABLE_ARCH_8) {\n return false;\n@@ -4230,10 +4237,23 @@ static bool op_stl(DisasContext *s, arg_STL *a, MemOp mop)\n \n addr = load_reg(s, a->rn);\n tmp = load_reg(s, a->rt);\n+ skip_monitor_event = gen_new_label();\n tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);\n gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), mop | MO_ALIGN);\n disas_set_da_iss(s, mop, a->rt | ISSIsAcqRel | ISSIsWrite);\n \n+ /*\n+ * We don't fully model the global monitor as it would be very\n+ * expensive for every memory access. However in the Arm ARM \"Use\n+ * of Wait for Event (WFE) and Send Event (SEV) with lock\" it does\n+ * give the example of using STL to clear a lock. So if a lock is\n+ * active trigger the global event register so we don't deadlock\n+ * while sleeping.\n+ */\n+ tcg_gen_brcondi_i64(TCG_COND_EQ, cpu_exclusive_addr, -1, skip_monitor_event);\n+ gen_global_event_reg();\n+ gen_set_label(skip_monitor_event);\n+\n return true;\n }\n \n","prefixes":["v2","29/31"]}