{"id":2226132,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2226132/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260422101043.1234229-4-alex.bennee@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260422101043.1234229-4-alex.bennee@linaro.org>","list_archive_url":null,"date":"2026-04-22T10:10:14","name":"[v2,03/31] target/arm: migrate FP/SIMD trap syndromes to registerfields","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"eb100e619f882b852a9a7e30e4a3b0106bdaca3b","submitter":{"id":39532,"url":"http://patchwork.ozlabs.org/api/1.2/people/39532/?format=json","name":"Alex Bennée","email":"alex.bennee@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260422101043.1234229-4-alex.bennee@linaro.org/mbox/","series":[{"id":500957,"url":"http://patchwork.ozlabs.org/api/1.2/series/500957/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500957","date":"2026-04-22T10:10:11","name":"target/arm: fully model WFxT instructions for A-profile","version":2,"mbox":"http://patchwork.ozlabs.org/series/500957/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2226132/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2226132/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=BWrMjJ72;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2a00:1450:4864:20::434;\n envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x434.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"The syn_simd_access trap was never used so remove it. We should only\nsee the COPROC encoding on v7 architectures.\n\nReviewed-by: Richard Henderson \nSigned-off-by: Alex Bennée \n\n---\nv2\n - use !is16_bit directly\n---\n target/arm/syndrome.h | 25 +++++++++++++++----------\n 1 file changed, 15 insertions(+), 10 deletions(-)","diff":"diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h\nindex 29462aa103c..72051443d59 100644\n--- a/target/arm/syndrome.h\n+++ b/target/arm/syndrome.h\n@@ -337,21 +337,26 @@ static inline uint32_t syn_cp15_rrt_trap(int cv, int cond, int opc1, int crm,\n return res;\n }\n \n+/*\n+ * ISS encoding for an exception from an access to a register of\n+ * instruction resulting from the FPEN or TFP traps.\n+ */\n+FIELD(FP_ISS, COPROC, 0, 4) /* ARMv7 only */\n+FIELD(FP_ISS, COND, 20, 4)\n+FIELD(FP_ISS, CV, 24, 1)\n+\n static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_16bit,\n int coproc)\n {\n /* AArch32 FP trap or any AArch64 FP/SIMD trap: TA == 0 */\n- return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT)\n- | (is_16bit ? 0 : ARM_EL_IL)\n- | (cv << 24) | (cond << 20) | coproc;\n-}\n+ uint32_t res = syn_set_ec(0, EC_ADVSIMDFPACCESSTRAP);\n+ res = FIELD_DP32(res, SYNDROME, IL, !is_16bit);\n \n-static inline uint32_t syn_simd_access_trap(int cv, int cond, bool is_16bit)\n-{\n- /* AArch32 SIMD trap: TA == 1 coproc == 0 */\n- return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT)\n- | (is_16bit ? 0 : ARM_EL_IL)\n- | (cv << 24) | (cond << 20) | (1 << 5);\n+ res = FIELD_DP32(res, FP_ISS, CV, cv);\n+ res = FIELD_DP32(res, FP_ISS, COND, cond);\n+ res = FIELD_DP32(res, FP_ISS, COPROC, coproc);\n+\n+ return res;\n }\n \n static inline uint32_t syn_sve_access_trap(void)\n","prefixes":["v2","03/31"]}