{"id":2226125,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2226125/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260422093549.407022-5-sherry.sun@nxp.com/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/1.2/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260422093549.407022-5-sherry.sun@nxp.com>","list_archive_url":null,"date":"2026-04-22T09:35:41","name":"[V14,04/12] PCI: imx6: Add support for parsing the reset property in new Root Port binding","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"e5122377224a87cc78912f93453456e22e5e2e0f","submitter":{"id":77063,"url":"http://patchwork.ozlabs.org/api/1.2/people/77063/?format=json","name":"Sherry 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","To":"robh@kernel.org,\n\tkrzk+dt@kernel.org,\n\tconor+dt@kernel.org,\n\tFrank.Li@nxp.com,\n\ts.hauer@pengutronix.de,\n\tkernel@pengutronix.de,\n\tfestevam@gmail.com,\n\tlpieralisi@kernel.org,\n\tkwilczynski@kernel.org,\n\tmani@kernel.org,\n\tbhelgaas@google.com,\n\thongxing.zhu@nxp.com,\n\tl.stach@pengutronix.de","Cc":"imx@lists.linux.dev,\n\tlinux-pci@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org,\n\tdevicetree@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org","Subject":"[PATCH V14 04/12] PCI: imx6: Add support for parsing the reset\n property in new Root Port binding","Date":"Wed, 22 Apr 2026 17:35:41 +0800","Message-Id":"<20260422093549.407022-5-sherry.sun@nxp.com>","X-Mailer":"git-send-email 2.37.1","In-Reply-To":"<20260422093549.407022-1-sherry.sun@nxp.com>","References":"<20260422093549.407022-1-sherry.sun@nxp.com>","Content-Transfer-Encoding":"8bit","Content-Type":"text/plain","X-ClientProxiedBy":"SG2PR01CA0140.apcprd01.prod.exchangelabs.com\n (2603:1096:4:8f::20) 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txLfvVBTkEG8qwIkwybwKKqKMYfx425TpyL9HFtgD8a+u5JUSYu+zilVhYtSTHsmzDYHWmS5B6uEJ3SqZtaaIJV1zlAcQFCmdf18dQN0EoN5B1GeEucCz00M2PWwTaqQCB69CSz1gLJCr9C2L/5tSBPxmC1mfIwa3kZVAx10AY+vSomh2AXLWiqbF0dj2xURdJu+QvuYnxUvXYyXT+6L+Z/kGZVyvwOmy52jyRyBlC1nupHu5Cs35H9l7P1TUH+4I7T1T/jDKy7vkKGmeZt6h3RwJSyCrGiidZfHccTjjWwFOCG8GGIYLlanuTjLC0mfXWUdZdbi1J2P1nDZ9yq05fmJo0HyY+8u2sSe/jIkSKRlyOWcACV55LWZsurP9lAoCKfGMc/HJ1dhuEskMH1LsX2z61kB2axt62YwiWLEMS2YrzG1VrwQswez9Owv0AaE/BBNaSRDSdQtthvf2BymjbiJOxws4jIs8aA9REUNohRCzXvWiY1OOYcB7QeZpysEWKaDpT/wl6KIHu1iNWnEm7DvySTjLhY0Bs8fE22N+RLvHjjyiX7ACPhjTC59fcTXGCWdNC5WVrDzmAKFssUr16iaUis64jQDj4frRpA4sARlnVMHH5h4qQYIAflFDf62LLsl1l2tezlQHJf0H4iaMaw5GQpWjH8Tk+mqjAqxc+e8UWTSFnP+7JZrdzw3HTO3SSb4QvvrFpqBaPphm5vD7kawCp2b48pWWMxQCH04i6isHoHrPr470N7rsYXkpqEXTz91b9/8WsVgbwYiRERZ6++fIxB/5TsXvq7XR/aUyV2xSlyABknv5fdNg2zmnPUQOACF6Z+6IpNbpg/Jhs7AjA6cnktzzVLjc7ZwiYvIXZWcS3TRVPpodKJ4aIEOincLemBv8Q0XE1Ujy28JGOggk73b69Xr0GYxfzSKbACOkAVofAANUOBMt1A7G2JzQc7cAoN2uvdkGIaNUb9f18iZbIjv8e2W3fOZqeT4slmX+Lgr8X2M13nr0mkKhJIvs76R7yPcUijRo9xT181lWompCzmuF6uu5G8HrRMJz3UTbH0glTnwggjT/7JVn2oeCZx/P7+WAy612REocNmmh+DgtTwR4DGXRHCwFGtnishNuiRpoyqVxucHrO3DsSEgt7HjHCzmgWUK6dEYGv2rg6v68/VF5Z6TcTUQOzh9lm+KJEBhCDAKmmT3oHPeLfmm8ZDB8M2tYTvOc0Rt4D2LafS1n8SQQ+e7umO+PRkzyF7uzul1lCQKK7LMdPFndd+XTEWV8xgq+hfOLXtuAJlm9BFWEdB4OKXlN6yRv+LHxIUakNrP00h4InIwBqaZWEcyEt1OuMgD4BNim2YRBtXNsdKED3ICYAD44p2x3XXvq9GknetBVExwKtjB1koG/WuEbMpZs9aGy+ALNavPkTjn8BlxNacTyebSSiLXE1zhnnSp5fvCzcWVX1FzS4p7a3RI6kkGeINPHfO2TN0FaCVh6CZyJovnwvxUEH//NB25jRBV7VU3sQcTox9O8ZrgcMYHXHSUo/upyCQ8p6Jl2lCJHymomQS6i6l+lffvZjRoqJ5F9C2rmnT4qMdG98QBWDN2NzTTUqiNfjr0ebjtgPzV1zN6H6hdY6UlBBVtVgMUEXBM4n2LQj3kKH25GVTft0caSlxRzdWnYLtPZ0YdYMRKZzzxwfCfnGr/2ZWAh2KKngmMKTe4Px1W6F9w5To8HEZ4JhkQFkuYdYhvWisK4xA4TxZwig==","X-OriginatorOrg":"nxp.com","X-MS-Exchange-CrossTenant-Network-Message-Id":"\n 508904dd-4a38-43bb-4fb5-08dea0525cf9","X-MS-Exchange-CrossTenant-AuthSource":"VI0PR04MB12114.eurprd04.prod.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Internal","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"22 Apr 2026 09:34:34.2366\n (UTC)","X-MS-Exchange-CrossTenant-FromEntityHeader":"Hosted","X-MS-Exchange-CrossTenant-Id":"686ea1d3-bc2b-4c6f-a92c-d99c5c301635","X-MS-Exchange-CrossTenant-MailboxType":"HOSTED","X-MS-Exchange-CrossTenant-UserPrincipalName":"\n DoBoFTvEK1xDqUVIBYP2XAertD412FNPNy7HrtH+rz5IBIjj8tLr/pERogNo08ihEkFQ5gIQ1ZXP1ttovGB7aQ==","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"PA2PR04MB10129"},"content":"The current DT binding for pci-imx6 specifies the 'reset-gpios' property\nin the host bridge node. However, the PERST# signal logically belongs to\nindividual Root Ports rather than the host bridge itself. This becomes\nimportant when supporting PCIe KeyE connector and PCI power control\nframework for pci-imx6 driver, which requires properties to be specified\nin Root Port nodes.\n\nAdd support for parsing 'reset-gpios' from Root Port nodes and the PCIe\nbridge nodes under the Root Port using the common helper\npci_host_common_parse_ports(), and update the reset GPIO handling to use\nthe parsed port list from bridge->ports. To maintain DT backwards\ncompatibility, fallback to the legacy method of parsing the host bridge\nnode if the reset property is not present in the Root Port nodes.\n\nSince now the reset GPIO is obtained with GPIOD_ASIS flag, it may be in\ninput mode, using gpiod_direction_output() instead of\ngpiod_set_value_cansleep() to ensure the reset GPIO is properly\nconfigured as output before setting its value.\n\nSigned-off-by: Sherry Sun \n---\n drivers/pci/controller/dwc/pci-imx6.c | 83 ++++++++++++++++++++++-----\n 1 file changed, 70 insertions(+), 13 deletions(-)","diff":"diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c\nindex 735127ed1455..a2742620279a 100644\n--- a/drivers/pci/controller/dwc/pci-imx6.c\n+++ b/drivers/pci/controller/dwc/pci-imx6.c\n@@ -34,6 +34,7 @@\n #include \n \n #include \"../../pci.h\"\n+#include \"../pci-host-common.h\"\n #include \"pcie-designware.h\"\n \n #define IMX8MQ_GPR_PCIE_REF_USE_PAD\t\tBIT(9)\n@@ -152,7 +153,6 @@ struct imx_lut_data {\n \n struct imx_pcie {\n \tstruct dw_pcie\t\t*pci;\n-\tstruct gpio_desc\t*reset_gpiod;\n \tstruct clk_bulk_data\t*clks;\n \tint\t\t\tnum_clks;\n \tbool\t\t\tsupports_clkreq;\n@@ -1224,6 +1224,41 @@ static void imx_pcie_disable_device(struct pci_host_bridge *bridge,\n \timx_pcie_remove_lut(imx_pcie, pci_dev_id(pdev));\n }\n \n+static int imx_pcie_parse_legacy_binding(struct imx_pcie *pcie)\n+{\n+\tstruct device *dev = pcie->pci->dev;\n+\tstruct pci_host_bridge *bridge = pcie->pci->pp.bridge;\n+\tstruct pci_host_port *port;\n+\tstruct pci_host_perst *perst;\n+\tstruct gpio_desc *reset;\n+\n+\treset = devm_gpiod_get_optional(dev, \"reset\", GPIOD_ASIS);\n+\tif (IS_ERR(reset))\n+\t\treturn PTR_ERR(reset);\n+\n+\tif (!reset)\n+\t\treturn 0;\n+\n+\tport = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);\n+\tif (!port)\n+\t\treturn -ENOMEM;\n+\n+\tperst = devm_kzalloc(dev, sizeof(*perst), GFP_KERNEL);\n+\tif (!perst)\n+\t\treturn -ENOMEM;\n+\n+\tINIT_LIST_HEAD(&port->perst);\n+\tperst->desc = reset;\n+\tINIT_LIST_HEAD(&perst->list);\n+\tlist_add_tail(&perst->list, &port->perst);\n+\n+\tINIT_LIST_HEAD(&port->list);\n+\tlist_add_tail(&port->list, &bridge->ports);\n+\n+\treturn devm_add_action_or_reset(dev, pci_host_common_delete_ports,\n+\t\t\t\t\t&bridge->ports);\n+}\n+\n static void imx_pcie_vpcie_aux_disable(void *data)\n {\n \tstruct regulator *vpcie_aux = data;\n@@ -1233,14 +1268,26 @@ static void imx_pcie_vpcie_aux_disable(void *data)\n \n static void imx_pcie_assert_perst(struct imx_pcie *imx_pcie, bool assert)\n {\n+\tstruct dw_pcie *pci = imx_pcie->pci;\n+\tstruct pci_host_bridge *bridge = pci->pp.bridge;\n+\tstruct pci_host_perst *perst;\n+\tstruct pci_host_port *port;\n+\n+\tif (!bridge || list_empty(&bridge->ports))\n+\t\treturn;\n+\n \tif (assert) {\n-\t\tgpiod_set_value_cansleep(imx_pcie->reset_gpiod, 1);\n+\t\tlist_for_each_entry(port, &bridge->ports, list) {\n+\t\t\tlist_for_each_entry(perst, &port->perst, list)\n+\t\t\t\tgpiod_direction_output(perst->desc, 1);\n+\t\t}\n \t} else {\n-\t\tif (imx_pcie->reset_gpiod) {\n-\t\t\tmsleep(PCIE_T_PVPERL_MS);\n-\t\t\tgpiod_set_value_cansleep(imx_pcie->reset_gpiod, 0);\n-\t\t\tmsleep(PCIE_RESET_CONFIG_WAIT_MS);\n+\t\tmdelay(PCIE_T_PVPERL_MS);\n+\t\tlist_for_each_entry(port, &bridge->ports, list) {\n+\t\t\tlist_for_each_entry(perst, &port->perst, list)\n+\t\t\t\tgpiod_direction_output(perst->desc, 0);\n \t\t}\n+\t\tmdelay(PCIE_RESET_CONFIG_WAIT_MS);\n \t}\n }\n \n@@ -1249,8 +1296,25 @@ static int imx_pcie_host_init(struct dw_pcie_rp *pp)\n \tstruct dw_pcie *pci = to_dw_pcie_from_pp(pp);\n \tstruct device *dev = pci->dev;\n \tstruct imx_pcie *imx_pcie = to_imx_pcie(pci);\n+\tstruct pci_host_bridge *bridge = pp->bridge;\n \tint ret;\n \n+\tif (bridge && list_empty(&bridge->ports)) {\n+\t\t/* Parse Root Port nodes if present */\n+\t\tret = pci_host_common_parse_ports(dev, bridge);\n+\t\tif (ret) {\n+\t\t\tif (ret != -ENODEV) {\n+\t\t\t\tdev_err(dev, \"Failed to parse Root Port nodes: %d\\n\", ret);\n+\t\t\t\treturn ret;\n+\t\t\t}\n+\n+\t\t\t/* Fallback to legacy binding for DT backwards compatibility */\n+\t\t\tret = imx_pcie_parse_legacy_binding(imx_pcie);\n+\t\t\tif (ret)\n+\t\t\t\treturn ret;\n+\t\t}\n+\t}\n+\n \timx_pcie_assert_perst(imx_pcie, true);\n \n \t/* Keep 3.3Vaux supply enabled for the entire PCIe controller lifecycle */\n@@ -1704,13 +1768,6 @@ static int imx_pcie_probe(struct platform_device *pdev)\n \t\t\treturn PTR_ERR(imx_pcie->phy_base);\n \t}\n \n-\t/* Fetch GPIOs */\n-\timx_pcie->reset_gpiod = devm_gpiod_get_optional(dev, \"reset\", GPIOD_OUT_HIGH);\n-\tif (IS_ERR(imx_pcie->reset_gpiod))\n-\t\treturn dev_err_probe(dev, PTR_ERR(imx_pcie->reset_gpiod),\n-\t\t\t\t \"unable to get reset gpio\\n\");\n-\tgpiod_set_consumer_name(imx_pcie->reset_gpiod, \"PCIe reset\");\n-\n \t/* Fetch clocks */\n \timx_pcie->num_clks = devm_clk_bulk_get_all(dev, &imx_pcie->clks);\n \tif (imx_pcie->num_clks < 0)\n","prefixes":["V14","04/12"]}