{"id":2225871,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2225871/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260421-mips-octeon-missing-insns-v2-v2-2-a0791df188c9@gmail.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260421-mips-octeon-missing-insns-v2-v2-2-a0791df188c9@gmail.com>","list_archive_url":null,"date":"2026-04-21T17:27:29","name":"[v2,02/13] target/mips: fix Octeon arithmetic destination handling","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"a43b20758bc73fa8331a4a341fe03f2ea7de94ad","submitter":{"id":66301,"url":"http://patchwork.ozlabs.org/api/1.2/people/66301/?format=json","name":"James Hilliard","email":"james.hilliard1@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260421-mips-octeon-missing-insns-v2-v2-2-a0791df188c9@gmail.com/mbox/","series":[{"id":500858,"url":"http://patchwork.ozlabs.org/api/1.2/series/500858/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500858","date":"2026-04-21T17:27:27","name":"target/mips: add missing Octeon user-mode support","version":2,"mbox":"http://patchwork.ozlabs.org/series/500858/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2225871/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2225871/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=BGOc3Edi;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=\"utf-8\"","Content-Transfer-Encoding":"8bit","Message-Id":"\n <20260421-mips-octeon-missing-insns-v2-v2-2-a0791df188c9@gmail.com>","References":"\n <20260421-mips-octeon-missing-insns-v2-v2-0-a0791df188c9@gmail.com>","In-Reply-To":"\n <20260421-mips-octeon-missing-insns-v2-v2-0-a0791df188c9@gmail.com>","To":"qemu-devel@nongnu.org","Cc":"Laurent Vivier ,\n Pierrick Bouvier , =?utf-8?q?Philippe_Mathieu?=\n\t=?utf-8?q?-Daud=C3=A9?= ,\n Aurelien Jarno ,\n Jiaxun Yang ,\n Aleksandar Rikalo , Huacai Chen ,\n James Hilliard ","X-Mailer":"b4 0.15.2","Received-SPF":"pass client-ip=2001:4860:4864:20::2b;\n envelope-from=james.hilliard1@gmail.com; helo=mail-oa1-x2b.google.com","X-Spam_score_int":"-17","X-Spam_score":"-1.8","X-Spam_bar":"-","X-Spam_report":"(-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"BADDU and DMUL write their results to rd, not rt. Avoid treating rt ==\n$zero as a nop, and route writes through gen_store_gpr() so rd == $zero\nis handled consistently.\n\nSigned-off-by: James Hilliard \n---\nChanges v1 -> v2:\n - Split the BADDU/DMUL destination handling fix out of the Octeon\n arithmetic instruction patch. (suggested by Philippe Mathieu-Daudé)\n---\n target/mips/tcg/octeon_translate.c | 12 +++++++-----\n 1 file changed, 7 insertions(+), 5 deletions(-)","diff":"diff --git a/target/mips/tcg/octeon_translate.c b/target/mips/tcg/octeon_translate.c\nindex b2eca29e06..41e0d770f5 100644\n--- a/target/mips/tcg/octeon_translate.c\n+++ b/target/mips/tcg/octeon_translate.c\n@@ -45,7 +45,7 @@ static bool trans_BADDU(DisasContext *ctx, arg_BADDU *a)\n {\n TCGv t0, t1;\n \n- if (a->rt == 0) {\n+ if (a->rd == 0) {\n /* nop */\n return true;\n }\n@@ -55,8 +55,9 @@ static bool trans_BADDU(DisasContext *ctx, arg_BADDU *a)\n gen_load_gpr(t0, a->rs);\n gen_load_gpr(t1, a->rt);\n \n- tcg_gen_add_tl(t0, t0, t1);\n- tcg_gen_andi_i64(cpu_gpr[a->rd], t0, 0xff);\n+ tcg_gen_add_i64(t0, t0, t1);\n+ tcg_gen_andi_i64(t0, t0, 0xff);\n+ gen_store_gpr(t0, a->rd);\n return true;\n }\n \n@@ -64,7 +65,7 @@ static bool trans_DMUL(DisasContext *ctx, arg_DMUL *a)\n {\n TCGv t0, t1;\n \n- if (a->rt == 0) {\n+ if (a->rd == 0) {\n /* nop */\n return true;\n }\n@@ -74,7 +75,8 @@ static bool trans_DMUL(DisasContext *ctx, arg_DMUL *a)\n gen_load_gpr(t0, a->rs);\n gen_load_gpr(t1, a->rt);\n \n- tcg_gen_mul_i64(cpu_gpr[a->rd], t0, t1);\n+ tcg_gen_mul_i64(t0, t0, t1);\n+ gen_store_gpr(t0, a->rd);\n return true;\n }\n \n","prefixes":["v2","02/13"]}