{"id":2225869,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2225869/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260421-mips-octeon-missing-insns-v2-v2-4-a0791df188c9@gmail.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260421-mips-octeon-missing-insns-v2-v2-4-a0791df188c9@gmail.com>","list_archive_url":null,"date":"2026-04-21T17:27:31","name":"[v2,04/13] target/mips: use explicit i64 TCG ops for Octeon translation","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"1c1d69d330fd9fd28fb5588e28ffad6d71096f11","submitter":{"id":66301,"url":"http://patchwork.ozlabs.org/api/1.2/people/66301/?format=json","name":"James Hilliard","email":"james.hilliard1@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260421-mips-octeon-missing-insns-v2-v2-4-a0791df188c9@gmail.com/mbox/","series":[{"id":500858,"url":"http://patchwork.ozlabs.org/api/1.2/series/500858/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500858","date":"2026-04-21T17:27:27","name":"target/mips: add missing Octeon user-mode support","version":2,"mbox":"http://patchwork.ozlabs.org/series/500858/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2225869/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2225869/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=hwfD3oZN;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=\"utf-8\"","Content-Transfer-Encoding":"7bit","Message-Id":"\n <20260421-mips-octeon-missing-insns-v2-v2-4-a0791df188c9@gmail.com>","References":"\n <20260421-mips-octeon-missing-insns-v2-v2-0-a0791df188c9@gmail.com>","In-Reply-To":"\n <20260421-mips-octeon-missing-insns-v2-v2-0-a0791df188c9@gmail.com>","To":"qemu-devel@nongnu.org","Cc":"Laurent Vivier ,\n Pierrick Bouvier , =?utf-8?q?Philippe_Mathieu?=\n\t=?utf-8?q?-Daud=C3=A9?= ,\n Aurelien Jarno ,\n Jiaxun Yang ,\n Aleksandar Rikalo , Huacai Chen ,\n James Hilliard ","X-Mailer":"b4 0.15.2","Received-SPF":"pass client-ip=2001:4860:4864:20::36;\n envelope-from=james.hilliard1@gmail.com; helo=mail-oa1-x36.google.com","X-Spam_score_int":"-17","X-Spam_score":"-1.8","X-Spam_bar":"-","X-Spam_report":"(-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Octeon instructions are only available on 64-bit CPUs. Use explicit i64\nTCG temporaries and operations in the existing Octeon translator paths,\nand reject 64-bit-only forms when decoding for a non-64-bit target.\n\nThis matches the architectural restriction directly and avoids depending\non target_ulong width in translator code that is only valid for MIPS64.\n\nSigned-off-by: James Hilliard \n---\n target/mips/tcg/octeon_translate.c | 76 +++++++++++++++++++++++---------------\n 1 file changed, 47 insertions(+), 29 deletions(-)","diff":"diff --git a/target/mips/tcg/octeon_translate.c b/target/mips/tcg/octeon_translate.c\nindex fce01eb196..73090ce6d8 100644\n--- a/target/mips/tcg/octeon_translate.c\n+++ b/target/mips/tcg/octeon_translate.c\n@@ -13,9 +13,15 @@\n /* Include the auto-generated decoder. */\n #include \"decode-octeon.c.inc\"\n \n+static bool octeon_check_64(DisasContext *ctx)\n+{\n+ check_mips_64(ctx);\n+ return ctx->base.is_jmp == DISAS_NEXT;\n+}\n+\n static bool trans_BBIT(DisasContext *ctx, arg_BBIT *a)\n {\n- TCGv p;\n+ TCGv_i64 p;\n \n if (ctx->hflags & MIPS_HFLAG_BMASK) {\n LOG_DISAS(\"Branch in delay / forbidden slot at PC 0x%\" VADDR_PRIx \"\\n\",\n@@ -25,14 +31,14 @@ static bool trans_BBIT(DisasContext *ctx, arg_BBIT *a)\n }\n \n /* Load needed operands */\n- TCGv t0 = tcg_temp_new();\n+ TCGv_i64 t0 = tcg_temp_new_i64();\n gen_load_gpr(t0, a->rs);\n \n- p = tcg_constant_tl(1ULL << a->p);\n+ p = tcg_constant_i64(1ULL << a->p);\n if (a->set) {\n- tcg_gen_and_tl(bcond, p, t0);\n+ tcg_gen_and_i64(bcond, p, t0);\n } else {\n- tcg_gen_andc_tl(bcond, p, t0);\n+ tcg_gen_andc_i64(bcond, p, t0);\n }\n \n ctx->hflags |= MIPS_HFLAG_BC;\n@@ -43,15 +49,15 @@ static bool trans_BBIT(DisasContext *ctx, arg_BBIT *a)\n \n static bool trans_BADDU(DisasContext *ctx, arg_BADDU *a)\n {\n- TCGv t0, t1;\n+ TCGv_i64 t0, t1;\n \n if (a->rd == 0) {\n /* nop */\n return true;\n }\n \n- t0 = tcg_temp_new();\n- t1 = tcg_temp_new();\n+ t0 = tcg_temp_new_i64();\n+ t1 = tcg_temp_new_i64();\n gen_load_gpr(t0, a->rs);\n gen_load_gpr(t1, a->rt);\n \n@@ -63,15 +69,19 @@ static bool trans_BADDU(DisasContext *ctx, arg_BADDU *a)\n \n static bool trans_DMUL(DisasContext *ctx, arg_DMUL *a)\n {\n- TCGv t0, t1;\n+ TCGv_i64 t0, t1;\n+\n+ if (!octeon_check_64(ctx)) {\n+ return true;\n+ }\n \n if (a->rd == 0) {\n /* nop */\n return true;\n }\n \n- t0 = tcg_temp_new();\n- t1 = tcg_temp_new();\n+ t0 = tcg_temp_new_i64();\n+ t1 = tcg_temp_new_i64();\n gen_load_gpr(t0, a->rs);\n gen_load_gpr(t1, a->rt);\n \n@@ -82,74 +92,78 @@ static bool trans_DMUL(DisasContext *ctx, arg_DMUL *a)\n \n static bool trans_EXTS(DisasContext *ctx, arg_EXTS *a)\n {\n- TCGv t0;\n+ TCGv_i64 t0;\n \n if (a->rt == 0) {\n /* nop */\n return true;\n }\n \n- t0 = tcg_temp_new();\n+ t0 = tcg_temp_new_i64();\n gen_load_gpr(t0, a->rs);\n- tcg_gen_sextract_tl(t0, t0, a->p, a->lenm1 + 1);\n+ tcg_gen_sextract_i64(t0, t0, a->p, a->lenm1 + 1);\n gen_store_gpr(t0, a->rt);\n return true;\n }\n \n static bool trans_CINS(DisasContext *ctx, arg_CINS *a)\n {\n- TCGv t0;\n+ TCGv_i64 t0;\n \n if (a->rt == 0) {\n /* nop */\n return true;\n }\n \n- t0 = tcg_temp_new();\n+ t0 = tcg_temp_new_i64();\n gen_load_gpr(t0, a->rs);\n- tcg_gen_deposit_z_tl(t0, t0, a->p, a->lenm1 + 1);\n+ tcg_gen_deposit_z_i64(t0, t0, a->p, a->lenm1 + 1);\n gen_store_gpr(t0, a->rt);\n return true;\n }\n \n static bool trans_POP(DisasContext *ctx, arg_POP *a)\n {\n- TCGv t0;\n+ TCGv_i64 t0;\n+\n+ if (a->dw && !octeon_check_64(ctx)) {\n+ return true;\n+ }\n \n if (a->rd == 0) {\n /* nop */\n return true;\n }\n \n- t0 = tcg_temp_new();\n+ t0 = tcg_temp_new_i64();\n gen_load_gpr(t0, a->rs);\n if (!a->dw) {\n tcg_gen_andi_i64(t0, t0, 0xffffffff);\n }\n- tcg_gen_ctpop_tl(t0, t0);\n+ tcg_gen_ctpop_i64(t0, t0);\n gen_store_gpr(t0, a->rd);\n return true;\n }\n \n static bool trans_seqne(DisasContext *ctx, const arg_cmp3 *a)\n {\n- TCGv t0, t1;\n+ TCGv_i64 t0, t1;\n \n if (a->rd == 0) {\n /* nop */\n return true;\n }\n \n- t0 = tcg_temp_new();\n- t1 = tcg_temp_new();\n+ t0 = tcg_temp_new_i64();\n+ t1 = tcg_temp_new_i64();\n \n gen_load_gpr(t0, a->rs);\n gen_load_gpr(t1, a->rt);\n \n if (a->ne) {\n- tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr[a->rd], t1, t0);\n+ tcg_gen_setcond_i64(TCG_COND_NE, cpu_gpr[a->rd], t1, t0);\n } else {\n- tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr[a->rd], t1, t0);\n+ tcg_gen_setcond_i64(TCG_COND_EQ, cpu_gpr[a->rd], t1, t0);\n }\n return true;\n }\n@@ -166,23 +180,23 @@ static bool trans_SNE(DisasContext *ctx, arg_cmp3 *a)\n \n static bool trans_seqnei(DisasContext *ctx, const arg_cmpi *a)\n {\n- TCGv t0;\n+ TCGv_i64 t0;\n \n if (a->rt == 0) {\n /* nop */\n return true;\n }\n \n- t0 = tcg_temp_new();\n+ t0 = tcg_temp_new_i64();\n \n gen_load_gpr(t0, a->rs);\n \n /* Sign-extend to 64 bit value */\n int64_t imm = a->imm;\n if (a->ne) {\n- tcg_gen_setcondi_tl(TCG_COND_NE, cpu_gpr[a->rt], t0, imm);\n+ tcg_gen_setcondi_i64(TCG_COND_NE, cpu_gpr[a->rt], t0, imm);\n } else {\n- tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr[a->rt], t0, imm);\n+ tcg_gen_setcondi_i64(TCG_COND_EQ, cpu_gpr[a->rt], t0, imm);\n }\n return true;\n }\n@@ -199,6 +213,10 @@ static bool trans_SNEI(DisasContext *ctx, arg_cmpi *a)\n \n static bool trans_lx(DisasContext *ctx, arg_lx *a, MemOp mop)\n {\n+ if (mop == MO_UQ && !octeon_check_64(ctx)) {\n+ return true;\n+ }\n+\n gen_lx(ctx, a->rd, a->base, a->index, mop);\n \n return true;\n","prefixes":["v2","04/13"]}