{"id":2225867,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2225867/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260421-mips-octeon-missing-insns-v2-v2-13-a0791df188c9@gmail.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260421-mips-octeon-missing-insns-v2-v2-13-a0791df188c9@gmail.com>","list_archive_url":null,"date":"2026-04-21T17:27:40","name":"[v2,13/13] target/mips: expose Octeon68XX floating-point support","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"9eeb1b1df7e9ea8770967c473b3ead3da328eaf8","submitter":{"id":66301,"url":"http://patchwork.ozlabs.org/api/1.2/people/66301/?format=json","name":"James Hilliard","email":"james.hilliard1@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260421-mips-octeon-missing-insns-v2-v2-13-a0791df188c9@gmail.com/mbox/","series":[{"id":500858,"url":"http://patchwork.ozlabs.org/api/1.2/series/500858/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500858","date":"2026-04-21T17:27:27","name":"target/mips: add missing Octeon user-mode support","version":2,"mbox":"http://patchwork.ozlabs.org/series/500858/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2225867/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2225867/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=rRB1NNKX;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=\"utf-8\"","Content-Transfer-Encoding":"8bit","Message-Id":"\n <20260421-mips-octeon-missing-insns-v2-v2-13-a0791df188c9@gmail.com>","References":"\n <20260421-mips-octeon-missing-insns-v2-v2-0-a0791df188c9@gmail.com>","In-Reply-To":"\n <20260421-mips-octeon-missing-insns-v2-v2-0-a0791df188c9@gmail.com>","To":"qemu-devel@nongnu.org","Cc":"Laurent Vivier ,\n Pierrick Bouvier , =?utf-8?q?Philippe_Mathieu?=\n\t=?utf-8?q?-Daud=C3=A9?= ,\n Aurelien Jarno ,\n Jiaxun Yang ,\n Aleksandar Rikalo , Huacai Chen ,\n James Hilliard ","X-Mailer":"b4 0.15.2","Received-SPF":"pass client-ip=2607:f8b0:4864:20::230;\n envelope-from=james.hilliard1@gmail.com; helo=mail-oi1-x230.google.com","X-Spam_score_int":"-17","X-Spam_score":"-1.8","X-Spam_bar":"-","X-Spam_report":"(-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Octeon68XX cores implement CP1. Advertise that in the CPU definition by\nsetting Config1.FP, enabling the writable Status bits, and providing the\nFCR0/FCR31 defaults used by this CPU model.\n\nThis lets guests observe the expected floating-point feature bits and\nuse CP1 with -cpu Octeon68XX.\n\nSigned-off-by: James Hilliard \n\n---\nChanges v1 -> v2:\n - Move this CPU-model correction into a separate final patch.\n (suggested by Philippe Mathieu-Daudé)\n---\n target/mips/cpu-defs.c.inc | 10 ++++++++--\n 1 file changed, 8 insertions(+), 2 deletions(-)","diff":"diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc\nindex d93b9d341a..6c084fcaea 100644\n--- a/target/mips/cpu-defs.c.inc\n+++ b/target/mips/cpu-defs.c.inc\n@@ -997,7 +997,8 @@ const mips_def_t mips_defs[] =\n .CP0_PRid = 0x000D9100,\n .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |\n (MMU_TYPE_R4000 << CP0C0_MT),\n- .CP0_Config1 = MIPS_CONFIG1 | (0x3F << CP0C1_MMU) |\n+ .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) |\n+ (0x3F << CP0C1_MMU) |\n (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |\n (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |\n (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),\n@@ -1011,7 +1012,12 @@ const mips_def_t mips_defs[] =\n .CP0_PageGrain = (1 << CP0PG_ELPA),\n .SYNCI_Step = 32,\n .CCRes = 2,\n- .CP0_Status_rw_bitmask = 0x12F8FFFF,\n+ .CP0_Status_rw_bitmask = 0x36F8FFFF,\n+ .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) |\n+ (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |\n+ (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),\n+ .CP1_fcr31 = 0,\n+ .CP1_fcr31_rw_bitmask = 0xFF83FFFF,\n .SEGBITS = 42,\n .PABITS = 49,\n .insn_flags = CPU_MIPS64R2 | INSN_OCTEON,\n","prefixes":["v2","13/13"]}