{"id":2225862,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2225862/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260421-mips-octeon-missing-insns-v2-v2-3-a0791df188c9@gmail.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260421-mips-octeon-missing-insns-v2-v2-3-a0791df188c9@gmail.com>","list_archive_url":null,"date":"2026-04-21T17:27:30","name":"[v2,03/13] target/mips: split Octeon SEQ/SNE decode","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"c27f5266ab7023f22ead2d568d2635ee00d488f1","submitter":{"id":66301,"url":"http://patchwork.ozlabs.org/api/1.2/people/66301/?format=json","name":"James Hilliard","email":"james.hilliard1@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260421-mips-octeon-missing-insns-v2-v2-3-a0791df188c9@gmail.com/mbox/","series":[{"id":500858,"url":"http://patchwork.ozlabs.org/api/1.2/series/500858/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500858","date":"2026-04-21T17:27:27","name":"target/mips: add missing Octeon user-mode support","version":2,"mbox":"http://patchwork.ozlabs.org/series/500858/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2225862/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2225862/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=f801x8Ja;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=\"utf-8\"","Content-Transfer-Encoding":"8bit","Message-Id":"\n <20260421-mips-octeon-missing-insns-v2-v2-3-a0791df188c9@gmail.com>","References":"\n <20260421-mips-octeon-missing-insns-v2-v2-0-a0791df188c9@gmail.com>","In-Reply-To":"\n <20260421-mips-octeon-missing-insns-v2-v2-0-a0791df188c9@gmail.com>","To":"qemu-devel@nongnu.org","Cc":"Laurent Vivier ,\n Pierrick Bouvier , =?utf-8?q?Philippe_Mathieu?=\n\t=?utf-8?q?-Daud=C3=A9?= ,\n Aurelien Jarno ,\n Jiaxun Yang ,\n Aleksandar Rikalo , Huacai Chen ,\n James Hilliard ","X-Mailer":"b4 0.15.2","Received-SPF":"pass client-ip=2607:f8b0:4864:20::c30;\n envelope-from=james.hilliard1@gmail.com; helo=mail-oo1-xc30.google.com","X-Spam_score_int":"-17","X-Spam_score":"-1.8","X-Spam_bar":"-","X-Spam_report":"(-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Decode the equality and inequality forms as explicit SEQ/SNE and\nSEQI/SNEI instructions rather than using shared generated SEQNE/SEQNEI\nentries.\n\nThe explicit decoder names match the architectural mnemonics, which\nmakes the translator entry points and trace/debug output easier to\ncorrelate with the instruction set.\n\nSigned-off-by: James Hilliard \n---\nChanges v1 -> v2:\n - Split the SEQ/SNE decode cleanup out of the Octeon arithmetic\n instruction patch. (suggested by Philippe Mathieu-Daudé)\n---\n target/mips/tcg/octeon.decode | 8 ++++++--\n target/mips/tcg/octeon_translate.c | 26 +++++++++++++++++++++++---\n 2 files changed, 29 insertions(+), 5 deletions(-)","diff":"diff --git a/target/mips/tcg/octeon.decode b/target/mips/tcg/octeon.decode\nindex 102a05860d..8a262feb1d 100644\n--- a/target/mips/tcg/octeon.decode\n+++ b/target/mips/tcg/octeon.decode\n@@ -30,6 +30,8 @@ BBIT 11 set:1 . 10 rs:5 ..... offset:s16 p=%bbit_p\n # SNEI rt, rs, immediate\n \n @r3 ...... rs:5 rt:5 rd:5 ..... ......\n+&cmp3 rs rt rd ne\n+&cmpi rs rt imm ne\n %bitfield_p 0:1 6:5\n @bitfield ...... rs:5 rt:5 lenm1:5 ..... ..... . p=%bitfield_p\n \n@@ -38,8 +40,10 @@ DMUL 011100 ..... ..... ..... 00000 000011 @r3\n EXTS 011100 ..... ..... ..... ..... 11101 . @bitfield\n CINS 011100 ..... ..... ..... ..... 11001 . @bitfield\n POP 011100 rs:5 00000 rd:5 00000 10110 dw:1\n-SEQNE 011100 rs:5 rt:5 rd:5 00000 10101 ne:1\n-SEQNEI 011100 rs:5 rt:5 imm:s10 10111 ne:1\n+SEQ 011100 rs:5 rt:5 rd:5 00000 101010 &cmp3 ne=0\n+SNE 011100 rs:5 rt:5 rd:5 00000 101011 &cmp3 ne=1\n+SEQI 011100 rs:5 rt:5 imm:s10 101110 &cmpi ne=0\n+SNEI 011100 rs:5 rt:5 imm:s10 101111 &cmpi ne=1\n \n &lx base index rd\n @lx ...... base:5 index:5 rd:5 ...... ..... &lx\ndiff --git a/target/mips/tcg/octeon_translate.c b/target/mips/tcg/octeon_translate.c\nindex 41e0d770f5..fce01eb196 100644\n--- a/target/mips/tcg/octeon_translate.c\n+++ b/target/mips/tcg/octeon_translate.c\n@@ -131,7 +131,7 @@ static bool trans_POP(DisasContext *ctx, arg_POP *a)\n return true;\n }\n \n-static bool trans_SEQNE(DisasContext *ctx, arg_SEQNE *a)\n+static bool trans_seqne(DisasContext *ctx, const arg_cmp3 *a)\n {\n TCGv t0, t1;\n \n@@ -154,7 +154,17 @@ static bool trans_SEQNE(DisasContext *ctx, arg_SEQNE *a)\n return true;\n }\n \n-static bool trans_SEQNEI(DisasContext *ctx, arg_SEQNEI *a)\n+static bool trans_SEQ(DisasContext *ctx, arg_cmp3 *a)\n+{\n+ return trans_seqne(ctx, a);\n+}\n+\n+static bool trans_SNE(DisasContext *ctx, arg_cmp3 *a)\n+{\n+ return trans_seqne(ctx, a);\n+}\n+\n+static bool trans_seqnei(DisasContext *ctx, const arg_cmpi *a)\n {\n TCGv t0;\n \n@@ -168,7 +178,7 @@ static bool trans_SEQNEI(DisasContext *ctx, arg_SEQNEI *a)\n gen_load_gpr(t0, a->rs);\n \n /* Sign-extend to 64 bit value */\n- target_ulong imm = a->imm;\n+ int64_t imm = a->imm;\n if (a->ne) {\n tcg_gen_setcondi_tl(TCG_COND_NE, cpu_gpr[a->rt], t0, imm);\n } else {\n@@ -177,6 +187,16 @@ static bool trans_SEQNEI(DisasContext *ctx, arg_SEQNEI *a)\n return true;\n }\n \n+static bool trans_SEQI(DisasContext *ctx, arg_cmpi *a)\n+{\n+ return trans_seqnei(ctx, a);\n+}\n+\n+static bool trans_SNEI(DisasContext *ctx, arg_cmpi *a)\n+{\n+ return trans_seqnei(ctx, a);\n+}\n+\n static bool trans_lx(DisasContext *ctx, arg_lx *a, MemOp mop)\n {\n gen_lx(ctx, a->rd, a->base, a->index, mop);\n","prefixes":["v2","03/13"]}