{"id":2225562,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2225562/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260421074204.2908422-3-frank.chang@sifive.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260421074204.2908422-3-frank.chang@sifive.com>","list_archive_url":null,"date":"2026-04-21T07:42:04","name":"[v2,2/2] target/riscv: Add standard B extension implied rule","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"293ee115d6d3f2922c5bf8a8f355e32c6f43f8ff","submitter":{"id":79604,"url":"http://patchwork.ozlabs.org/api/1.2/people/79604/?format=json","name":"Frank Chang","email":"frank.chang@sifive.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260421074204.2908422-3-frank.chang@sifive.com/mbox/","series":[{"id":500751,"url":"http://patchwork.ozlabs.org/api/1.2/series/500751/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500751","date":"2026-04-21T07:42:02","name":"Add the implied rules for G and B extensions","version":2,"mbox":"http://patchwork.ozlabs.org/series/500751/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2225562/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2225562/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=sifive.com header.i=@sifive.com header.a=rsa-sha256\n header.s=google header.b=kdoVf6Am;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-pl1-x62f.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Frank Chang \n\nAdd the missing implied rule for standard B extension.\nStandard B extension implies Zba, Zbb, Zbs extensions.\nriscv_cpu_validate_b() is also removed as Zba, Zbb, Zbs extensions\ncan be enabled by the implied rule.\n\nRISC-V B spec: https://github.com/riscv/riscv-b\n\nReviewed-by: Jerry Zhang Jian \nReviewed-by: Jim Shu \nReviewed-by: Alistair Francis \nReviewed-by: Daniel Henrique Barboza \nSigned-off-by: Frank Chang \n---\n target/riscv/cpu.c | 14 +++++++++++++-\n target/riscv/tcg/tcg-cpu.c | 33 ---------------------------------\n 2 files changed, 13 insertions(+), 34 deletions(-)","diff":"diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c\nindex 7978b4fad43..37a328f2df7 100644\n--- a/target/riscv/cpu.c\n+++ b/target/riscv/cpu.c\n@@ -2259,6 +2259,17 @@ static RISCVCPUImpliedExtsRule RVG_IMPLIED = {\n },\n };\n \n+static RISCVCPUImpliedExtsRule RVB_IMPLIED = {\n+ .is_misa = true,\n+ .ext = RVB,\n+ .implied_multi_exts = {\n+ CPU_CFG_OFFSET(ext_zba), CPU_CFG_OFFSET(ext_zbb),\n+ CPU_CFG_OFFSET(ext_zbs),\n+\n+ RISCV_IMPLIED_EXTS_RULE_END\n+ },\n+};\n+\n static RISCVCPUImpliedExtsRule ZCB_IMPLIED = {\n .ext = CPU_CFG_OFFSET(ext_zcb),\n .implied_multi_exts = {\n@@ -2646,7 +2657,8 @@ static RISCVCPUImpliedExtsRule ZVFBFA_IMPLIED = {\n \n RISCVCPUImpliedExtsRule *riscv_misa_ext_implied_rules[] = {\n &RVA_IMPLIED, &RVD_IMPLIED, &RVF_IMPLIED,\n- &RVM_IMPLIED, &RVV_IMPLIED, &RVG_IMPLIED, NULL\n+ &RVM_IMPLIED, &RVV_IMPLIED, &RVG_IMPLIED,\n+ &RVB_IMPLIED, NULL\n };\n \n RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[] = {\ndiff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c\nindex 840ef82350d..7255f73f5a2 100644\n--- a/target/riscv/tcg/tcg-cpu.c\n+++ b/target/riscv/tcg/tcg-cpu.c\n@@ -532,35 +532,6 @@ static void riscv_cpu_update_named_features(RISCVCPU *cpu)\n cpu->cfg.ext_ziccrse = cpu->cfg.has_priv_1_11;\n }\n \n-static void riscv_cpu_validate_b(RISCVCPU *cpu)\n-{\n- const char *warn_msg = \"RVB mandates disabled extension %s\";\n-\n- if (!cpu->cfg.ext_zba) {\n- if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zba))) {\n- cpu->cfg.ext_zba = true;\n- } else {\n- warn_report(warn_msg, \"zba\");\n- }\n- }\n-\n- if (!cpu->cfg.ext_zbb) {\n- if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zbb))) {\n- cpu->cfg.ext_zbb = true;\n- } else {\n- warn_report(warn_msg, \"zbb\");\n- }\n- }\n-\n- if (!cpu->cfg.ext_zbs) {\n- if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zbs))) {\n- cpu->cfg.ext_zbs = true;\n- } else {\n- warn_report(warn_msg, \"zbs\");\n- }\n- }\n-}\n-\n /*\n * Check consistency between chosen extensions while setting\n * cpu->cfg accordingly.\n@@ -571,10 +542,6 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)\n CPURISCVState *env = &cpu->env;\n Error *local_err = NULL;\n \n- if (riscv_has_ext(env, RVB)) {\n- riscv_cpu_validate_b(cpu);\n- }\n-\n if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) {\n error_setg(errp,\n \"I and E extensions are incompatible\");\n","prefixes":["v2","2/2"]}