{"id":2225507,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2225507/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260421053140.752059-11-joel@jms.id.au/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260421053140.752059-11-joel@jms.id.au>","list_archive_url":null,"date":"2026-04-21T05:31:35","name":"[v3,10/13] hw/riscv/atlantis: Add PCIe controller","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"e34c1ea791ba500ee0ee8f244ef48f22c70aecb9","submitter":{"id":48628,"url":"http://patchwork.ozlabs.org/api/1.2/people/48628/?format=json","name":"Joel Stanley","email":"joel@jms.id.au"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260421053140.752059-11-joel@jms.id.au/mbox/","series":[{"id":500733,"url":"http://patchwork.ozlabs.org/api/1.2/series/500733/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500733","date":"2026-04-21T05:31:26","name":"hw/riscv: Add the Tenstorrent Atlantis machine","version":3,"mbox":"http://patchwork.ozlabs.org/series/500733/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2225507/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2225507/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=J3Xox+Ep;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g0B0D6WvJz1yCv\n\tfor ; Tue, 21 Apr 2026 15:35:40 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wF3kO-0000lr-EN; Tue, 21 Apr 2026 01:34:08 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wF3k8-0000az-QR\n for qemu-devel@nongnu.org; Tue, 21 Apr 2026 01:33:55 -0400","from mail-pj1-x102f.google.com ([2607:f8b0:4864:20::102f])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wF3k6-0004VA-Kh\n for qemu-devel@nongnu.org; Tue, 21 Apr 2026 01:33:52 -0400","by mail-pj1-x102f.google.com with SMTP id\n 98e67ed59e1d1-3567e2b4159so2538939a91.0\n for ; Mon, 20 Apr 2026 22:33:50 -0700 (PDT)","from donnager-debian.. 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qemu-riscv@nongnu.org, qemu-devel@nongnu.org","Subject":"[PATCH v3 10/13] hw/riscv/atlantis: Add PCIe controller","Date":"Tue, 21 Apr 2026 15:31:35 +1000","Message-ID":"<20260421053140.752059-11-joel@jms.id.au>","X-Mailer":"git-send-email 2.47.3","In-Reply-To":"<20260421053140.752059-1-joel@jms.id.au>","References":"<20260421053140.752059-1-joel@jms.id.au>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2607:f8b0:4864:20::102f;\n envelope-from=joel.stan@gmail.com; helo=mail-pj1-x102f.google.com","X-Spam_score_int":"-16","X-Spam_score":"-1.7","X-Spam_bar":"-","X-Spam_report":"(-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.001,\n FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=no autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Nicholas Piggin \n\ntt-atlantis is likely to use a generic ECAM compatible PCIe memory map,\nso gpex is not far off the OS programming model\n\nSigned-off-by: Nicholas Piggin \nSigned-off-by: Joel Stanley \n---\nv3: Avoid leaks in the dt string allocation\n---\n include/hw/riscv/tt_atlantis.h | 2 +\n hw/riscv/tt_atlantis.c | 225 ++++++++++++++++++++++++++++++++-\n hw/riscv/Kconfig | 2 +\n 3 files changed, 228 insertions(+), 1 deletion(-)","diff":"diff --git a/include/hw/riscv/tt_atlantis.h b/include/hw/riscv/tt_atlantis.h\nindex f7f79e9f2c53..c0a0827a5167 100644\n--- a/include/hw/riscv/tt_atlantis.h\n+++ b/include/hw/riscv/tt_atlantis.h\n@@ -28,6 +28,7 @@ struct TTAtlantisState {\n \n RISCVHartArrayState soc;\n DeviceState *irqchip;\n+ GPEXHost gpex_host;\n \n int fdt_size;\n };\n@@ -39,6 +40,7 @@ enum {\n TT_ATL_UART2_IRQ = 40,\n TT_ATL_UART3_IRQ = 41,\n TT_ATL_UART4_IRQ = 42,\n+ TT_ATL_PCIE0_INTA_IRQ = 96,\n };\n \n enum {\ndiff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c\nindex a556ff79c8c8..e1753d3c1f18 100644\n--- a/hw/riscv/tt_atlantis.c\n+++ b/hw/riscv/tt_atlantis.c\n@@ -27,6 +27,7 @@\n #include \"hw/intc/riscv_aclint.h\"\n #include \"hw/intc/riscv_aplic.h\"\n #include \"hw/misc/pvpanic.h\"\n+#include \"hw/pci-host/gpex.h\"\n \n #include \"system/system.h\"\n #include \"system/device_tree.h\"\n@@ -70,6 +71,9 @@ static const MemMapEntry tt_atlantis_memmap[] = {\n [TT_ATL_PCIE_ECAM1] = { 0x01120000000, 0x10000000 },\n [TT_ATL_PCIE_ECAM2] = { 0x01130000000, 0x10000000 },\n [TT_ATL_PCIE_MMIO0] = { 0x10000000000, 0x10000000000 },\n+ [TT_ATL_PCIE_PIO0] = { 0x10000000000, 0x10000 }, /* qemu only */\n+ [TT_ATL_PCIE_MMIO0_32] = { 0x10004000000, 0x4000000 }, /* qemu only */\n+ [TT_ATL_PCIE_MMIO0_64] = { 0x10010000000, 0x0fff0000000 }, /* qemu only */\n [TT_ATL_PCIE_MMIO1] = { 0x20000000000, 0x10000000000 },\n [TT_ATL_PCIE_MMIO2] = { 0x30000000000, 0x10000000000 },\n };\n@@ -80,6 +84,59 @@ static uint32_t next_phandle(void)\n return phandle++;\n }\n \n+static void create_pcie_irq_map(void *fdt, char *nodename, int legacy_irq,\n+ uint32_t irqchip_phandle)\n+{\n+ int pin, dev;\n+ uint32_t irq_map_stride = 0;\n+ uint32_t full_irq_map[PCI_NUM_PINS * PCI_NUM_PINS *\n+ FDT_MAX_INT_MAP_WIDTH] = {};\n+ uint32_t *irq_map = full_irq_map;\n+\n+ /*\n+ * This code creates a standard swizzle of interrupts such that\n+ * each device's first interrupt is based on it's PCI_SLOT number.\n+ * (See pci_swizzle_map_irq_fn())\n+ *\n+ * We only need one entry per interrupt in the table (not one per\n+ * possible slot) seeing the interrupt-map-mask will allow the table\n+ * to wrap to any number of devices.\n+ */\n+ for (dev = 0; dev < PCI_NUM_PINS; dev++) {\n+ int devfn = dev * 0x8;\n+\n+ for (pin = 0; pin < PCI_NUM_PINS; pin++) {\n+ int irq_nr = legacy_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS);\n+ int i = 0;\n+\n+ /* Fill PCI address cells */\n+ irq_map[i] = cpu_to_be32(devfn << 8);\n+ i += FDT_PCI_ADDR_CELLS;\n+\n+ /* Fill PCI Interrupt cells */\n+ irq_map[i] = cpu_to_be32(pin + 1);\n+ i += FDT_PCI_INT_CELLS;\n+\n+ /* Fill interrupt controller phandle and cells */\n+ irq_map[i++] = cpu_to_be32(irqchip_phandle);\n+ irq_map[i++] = cpu_to_be32(irq_nr);\n+ irq_map[i++] = cpu_to_be32(0x4);\n+\n+ if (!irq_map_stride) {\n+ irq_map_stride = i;\n+ }\n+ irq_map += irq_map_stride;\n+ }\n+ }\n+\n+ qemu_fdt_setprop(fdt, nodename, \"interrupt-map\", full_irq_map,\n+ PCI_NUM_PINS * PCI_NUM_PINS *\n+ irq_map_stride * sizeof(uint32_t));\n+\n+ qemu_fdt_setprop_cells(fdt, nodename, \"interrupt-map-mask\",\n+ 0x1800, 0, 0, 0x7);\n+}\n+\n static void create_fdt_cpus(TTAtlantisState *s, uint32_t *intc_phandles)\n {\n uint32_t cpu_phandle;\n@@ -320,6 +377,54 @@ static void create_fdt_cpu(TTAtlantisState *s, const MemMapEntry *memmap,\n IRQ_S_EXT, s->soc.num_harts);\n }\n \n+static void create_fdt_pcie(void *fdt,\n+ const MemMapEntry *mem_ecam,\n+ const MemMapEntry *mem_pio,\n+ const MemMapEntry *mem_mmio32,\n+ const MemMapEntry *mem_mmio64,\n+ int legacy_irq,\n+ uint32_t aplic_s_phandle,\n+ uint32_t imsic_s_phandle)\n+{\n+ g_autofree char *name = g_strdup_printf(\"/soc/pci@%\"HWADDR_PRIX,\n+ mem_ecam->base);\n+\n+ qemu_fdt_setprop_cell(fdt, name, \"#address-cells\", FDT_PCI_ADDR_CELLS);\n+ qemu_fdt_setprop_cell(fdt, name, \"#interrupt-cells\", FDT_PCI_INT_CELLS);\n+ qemu_fdt_setprop_cell(fdt, name, \"#size-cells\", 0x2);\n+ qemu_fdt_setprop_string(fdt, name, \"compatible\", \"pci-host-ecam-generic\");\n+ qemu_fdt_setprop_string(fdt, name, \"device_type\", \"pci\");\n+ qemu_fdt_setprop_cells(fdt, name, \"bus-range\", 0,\n+ mem_ecam->size / PCIE_MMCFG_SIZE_MIN - 1);\n+ qemu_fdt_setprop(fdt, name, \"dma-coherent\", NULL, 0);\n+ qemu_fdt_setprop_cell(fdt, name, \"msi-parent\", imsic_s_phandle);\n+\n+ qemu_fdt_setprop_sized_cells(fdt, name, \"reg\",\n+ 2, mem_ecam->base,\n+ 2, mem_ecam->size);\n+ if (!(mem_mmio32->base & 0xffffffffUL)) {\n+ /* XXX: this is a silly hack because it would collide with PIO */\n+ error_report(\"mmio32 base must not be 0 mod 2^32\");\n+ exit(1);\n+ }\n+ uint32_t flags = FDT_PCI_RANGE_MMIO_64BIT | FDT_PCI_RANGE_PREFETCHABLE;\n+ qemu_fdt_setprop_sized_cells(fdt, name, \"ranges\",\n+ 1, FDT_PCI_RANGE_IOPORT,\n+ 2, 0x0,\n+ 2, mem_pio->base,\n+ 2, mem_pio->size,\n+ 1, FDT_PCI_RANGE_MMIO,\n+ 2, (mem_mmio32->base & 0xffffffffUL),\n+ 2, mem_mmio32->base,\n+ 2, mem_mmio32->size,\n+ 1, flags,\n+ 2, mem_mmio64->base,\n+ 2, mem_mmio64->base,\n+ 2, mem_mmio64->size);\n+\n+ create_pcie_irq_map(fdt, name, legacy_irq, aplic_s_phandle);\n+}\n+\n static void create_fdt_reset(void *fdt, const MemMapEntry *mem)\n {\n uint32_t syscon_phandle = next_phandle();\n@@ -385,6 +490,14 @@ static void finalize_fdt(TTAtlantisState *s)\n * aplic_s_phandle);\n */\n \n+ create_fdt_pcie(fdt,\n+ &s->memmap[TT_ATL_PCIE_ECAM0],\n+ &s->memmap[TT_ATL_PCIE_PIO0],\n+ &s->memmap[TT_ATL_PCIE_MMIO0_32],\n+ &s->memmap[TT_ATL_PCIE_MMIO0_64],\n+ TT_ATL_PCIE0_INTA_IRQ,\n+ aplic_s_phandle, imsic_s_phandle);\n+\n create_fdt_reset(fdt, &s->memmap[TT_ATL_SYSCON]);\n \n create_fdt_uart(fdt, &s->memmap[TT_ATL_UART0], TT_ATL_UART0_IRQ,\n@@ -395,7 +508,7 @@ static void create_fdt(TTAtlantisState *s)\n {\n MachineState *ms = MACHINE(s);\n uint8_t rng_seed[32];\n- g_autofree char *name = NULL;\n+ char *name;\n void *fdt;\n \n fdt = create_device_tree(&s->fdt_size);\n@@ -417,6 +530,25 @@ static void create_fdt(TTAtlantisState *s)\n qemu_fdt_setprop_cell(fdt, \"/soc\", \"#size-cells\", 0x2);\n qemu_fdt_setprop_cell(fdt, \"/soc\", \"#address-cells\", 0x2);\n \n+ /*\n+ * The \"/soc/pci@...\" node is needed for PCIE hotplugs\n+ * that might happen before finalize_fdt().\n+ */\n+ name = g_strdup_printf(\"/soc/pci@%\"HWADDR_PRIX,\n+ s->memmap[TT_ATL_PCIE_ECAM0].base);\n+ qemu_fdt_add_subnode(fdt, name);\n+ g_free(name);\n+\n+ name = g_strdup_printf(\"/soc/pci@%\"HWADDR_PRIX,\n+ s->memmap[TT_ATL_PCIE_ECAM1].base);\n+ qemu_fdt_add_subnode(fdt, name);\n+ g_free(name);\n+\n+ name = g_strdup_printf(\"/soc/pci@%\"HWADDR_PRIX,\n+ s->memmap[TT_ATL_PCIE_ECAM2].base);\n+ qemu_fdt_add_subnode(fdt, name);\n+ g_free(name);\n+\n qemu_fdt_add_subnode(fdt, \"/chosen\");\n \n /* Pass seed to RNG */\n@@ -429,6 +561,93 @@ static void create_fdt(TTAtlantisState *s)\n create_fdt_pmu(s);\n }\n \n+static void gpex_pcie_init_one(TTAtlantisState *s, GPEXHost *gpex_host,\n+ MemoryRegion *mr,\n+ const MemMapEntry *mem_ecam,\n+ const MemMapEntry *mem_pio,\n+ const MemMapEntry *mem_mmio32,\n+ const MemMapEntry *mem_mmio64,\n+ int legacy_irq)\n+{\n+ DeviceState *dev;\n+ Object *obj;\n+ MemoryRegion *ecam_alias, *ecam_reg;\n+ MemoryRegion *mmio32_alias, *mmio64_alias, *mmio_reg;\n+ hwaddr ecam_base = mem_ecam->base;\n+ hwaddr ecam_size = mem_ecam->size;\n+ hwaddr pio_base = mem_pio->base;\n+ hwaddr pio_size = mem_pio->size;\n+ hwaddr mmio32_base = mem_mmio32->base;\n+ hwaddr mmio32_size = mem_mmio32->size;\n+ hwaddr mmio64_base = mem_mmio64->base;\n+ hwaddr mmio64_size = mem_mmio64->size;\n+ qemu_irq irq;\n+ char name[16];\n+ int i;\n+\n+ snprintf(name, sizeof(name), \"pcie\");\n+ object_initialize_child(OBJECT(s), name, gpex_host, TYPE_GPEX_HOST);\n+ dev = DEVICE(gpex_host);\n+ obj = OBJECT(dev);\n+\n+ object_property_set_uint(obj, PCI_HOST_ECAM_BASE, ecam_base, &error_abort);\n+ object_property_set_int(obj, PCI_HOST_ECAM_SIZE, ecam_size, &error_abort);\n+ object_property_set_uint(obj, PCI_HOST_BELOW_4G_MMIO_BASE, mmio32_base,\n+ &error_abort);\n+ object_property_set_int(obj, PCI_HOST_BELOW_4G_MMIO_SIZE, mmio32_size,\n+ &error_abort);\n+ object_property_set_uint(obj, PCI_HOST_ABOVE_4G_MMIO_BASE, mmio64_base,\n+ &error_abort);\n+ object_property_set_int(obj, PCI_HOST_ABOVE_4G_MMIO_SIZE, mmio64_size,\n+ &error_abort);\n+ object_property_set_uint(obj, PCI_HOST_PIO_BASE, pio_base, &error_abort);\n+ object_property_set_int(obj, PCI_HOST_PIO_SIZE, pio_size, &error_abort);\n+\n+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);\n+\n+ ecam_alias = g_new0(MemoryRegion, 1);\n+ ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);\n+ snprintf(name, sizeof(name), \"pcie.ecam\");\n+ memory_region_init_alias(ecam_alias, obj, name,\n+ ecam_reg, 0, ecam_size);\n+ memory_region_add_subregion(mr, ecam_base, ecam_alias);\n+\n+ mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);\n+\n+ mmio32_alias = g_new0(MemoryRegion, 1);\n+ snprintf(name, sizeof(name), \"pcie.mmio32\");\n+ memory_region_init_alias(mmio32_alias, obj, name,\n+ mmio_reg, mmio32_base & 0xffffffffUL, mmio32_size);\n+ memory_region_add_subregion(mr, mmio32_base, mmio32_alias);\n+\n+ mmio64_alias = g_new0(MemoryRegion, 1);\n+ snprintf(name, sizeof(name), \"pcie.mmio64\");\n+ memory_region_init_alias(mmio64_alias, obj, name,\n+ mmio_reg, mmio64_base, mmio64_size);\n+ memory_region_add_subregion(mr, mmio64_base, mmio64_alias);\n+\n+ sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base);\n+\n+ for (i = 0; i < PCI_NUM_PINS; i++) {\n+ irq = qdev_get_gpio_in(s->irqchip, legacy_irq + i);\n+\n+ sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq);\n+ gpex_set_irq_num(GPEX_HOST(dev), i, legacy_irq + i);\n+ }\n+\n+ gpex_host->gpex_cfg.bus = PCI_HOST_BRIDGE(dev)->bus;\n+}\n+\n+static void gpex_pcie_init(TTAtlantisState *s, MemoryRegion *mr)\n+{\n+ gpex_pcie_init_one(s, &s->gpex_host, mr,\n+ &s->memmap[TT_ATL_PCIE_ECAM0],\n+ &s->memmap[TT_ATL_PCIE_PIO0],\n+ &s->memmap[TT_ATL_PCIE_MMIO0_32],\n+ &s->memmap[TT_ATL_PCIE_MMIO0_64],\n+ TT_ATL_PCIE0_INTA_IRQ);\n+}\n+\n static DeviceState *create_reboot_device(const MemMapEntry *mem)\n {\n DeviceState *dev = qdev_new(TYPE_PVPANIC_MMIO_DEVICE);\n@@ -588,6 +807,9 @@ static void tt_atlantis_machine_init(MachineState *machine)\n s->fw_cfg = create_fw_cfg(&s->memmap[TT_ATL_FW_CFG], machine->smp.cpus);\n rom_set_fw(s->fw_cfg);\n \n+ /* PCIe */\n+ gpex_pcie_init(s, system_memory);\n+\n /* Reboot and exit */\n create_reboot_device(&s->memmap[TT_ATL_SYSCON]);\n \n@@ -623,6 +845,7 @@ static void tt_atlantis_machine_class_init(ObjectClass *oc, const void *data)\n mc->default_cpu_type = TYPE_RISCV_CPU_TT_ASCALON;\n mc->block_default_type = IF_VIRTIO;\n mc->no_cdrom = 1;\n+ mc->pci_allow_0_address = true;\n mc->default_ram_id = \"tt_atlantis.ram\";\n }\n \ndiff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig\nindex 0601ae1a7494..2ddee591eb90 100644\n--- a/hw/riscv/Kconfig\n+++ b/hw/riscv/Kconfig\n@@ -129,6 +129,8 @@ config TENSTORRENT\n select DEVICE_TREE\n select RISCV_NUMA\n select PVPANIC_MMIO\n+ select PCI\n+ select PCI_EXPRESS_GENERIC_BRIDGE\n select SERIAL_MM\n select RISCV_ACLINT\n select RISCV_APLIC\n","prefixes":["v3","10/13"]}