{"id":2225506,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2225506/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260421053140.752059-3-joel@jms.id.au/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260421053140.752059-3-joel@jms.id.au>","list_archive_url":null,"date":"2026-04-21T05:31:27","name":"[v3,02/13] hw/riscv/boot: Describe discontiguous memory in boot_info","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"2702c3381f3c9646bfe44a1315e15e50c9bc3c1a","submitter":{"id":48628,"url":"http://patchwork.ozlabs.org/api/1.2/people/48628/?format=json","name":"Joel Stanley","email":"joel@jms.id.au"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260421053140.752059-3-joel@jms.id.au/mbox/","series":[{"id":500733,"url":"http://patchwork.ozlabs.org/api/1.2/series/500733/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500733","date":"2026-04-21T05:31:26","name":"hw/riscv: Add the Tenstorrent Atlantis machine","version":3,"mbox":"http://patchwork.ozlabs.org/series/500733/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2225506/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2225506/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=Zx/F43Is;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g0B0B4bvZz1yCv\n\tfor ; Tue, 21 Apr 2026 15:35:38 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wF3jb-0000QE-D2; Tue, 21 Apr 2026 01:33:20 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wF3jX-0000Pd-Og\n for qemu-devel@nongnu.org; Tue, 21 Apr 2026 01:33:15 -0400","from mail-pj1-x1030.google.com ([2607:f8b0:4864:20::1030])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wF3jW-0004P0-42\n for qemu-devel@nongnu.org; Tue, 21 Apr 2026 01:33:15 -0400","by mail-pj1-x1030.google.com with SMTP id\n 98e67ed59e1d1-356337f058aso2458593a91.2\n for ; Mon, 20 Apr 2026 22:33:13 -0700 (PDT)","from donnager-debian.. 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Provide an interface for\nmachines to describe a discontiguous low/high RAM scheme for this\npurpose.\n\nSigned-off-by: Nicholas Piggin \nReviewed-by: Daniel Henrique Barboza \nSigned-off-by: Joel Stanley \n---\n include/hw/riscv/boot.h | 7 +++++++\n hw/riscv/boot.c | 11 +++++++++++\n 2 files changed, 18 insertions(+)","diff":"diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h\nindex f00b3ca12245..115e3222174f 100644\n--- a/include/hw/riscv/boot.h\n+++ b/include/hw/riscv/boot.h\n@@ -28,6 +28,10 @@\n #define RISCV64_BIOS_BIN \"opensbi-riscv64-generic-fw_dynamic.bin\"\n \n typedef struct RISCVBootInfo {\n+ /* First contiguous RAM region. If size is zero then assume entire RAM */\n+ hwaddr ram_low_start;\n+ hwaddr ram_low_size;\n+\n ssize_t kernel_size;\n hwaddr image_low_addr;\n hwaddr image_high_addr;\n@@ -43,6 +47,9 @@ bool riscv_is_32bit(RISCVHartArrayState *harts);\n char *riscv_plic_hart_config_string(int hart_count);\n \n void riscv_boot_info_init(RISCVBootInfo *info, RISCVHartArrayState *harts);\n+void riscv_boot_info_init_discontig_mem(RISCVBootInfo *info,\n+ RISCVHartArrayState *harts,\n+ hwaddr start, hwaddr size);\n vaddr riscv_calc_kernel_start_addr(RISCVBootInfo *info,\n hwaddr firmware_end_addr);\n hwaddr riscv_find_and_load_firmware(MachineState *machine,\ndiff --git a/hw/riscv/boot.c b/hw/riscv/boot.c\nindex 9086793b7a7b..5c9547429a36 100644\n--- a/hw/riscv/boot.c\n+++ b/hw/riscv/boot.c\n@@ -69,11 +69,22 @@ char *riscv_plic_hart_config_string(int hart_count)\n \n void riscv_boot_info_init(RISCVBootInfo *info, RISCVHartArrayState *harts)\n {\n+ info->ram_low_start = 0;\n+ info->ram_low_size = 0;\n info->kernel_size = 0;\n info->initrd_size = 0;\n info->is_32bit = riscv_is_32bit(harts);\n }\n \n+void riscv_boot_info_init_discontig_mem(RISCVBootInfo *info,\n+ RISCVHartArrayState *harts,\n+ hwaddr start, hwaddr size)\n+{\n+ riscv_boot_info_init(info, harts);\n+ info->ram_low_start = start;\n+ info->ram_low_size = size;\n+}\n+\n vaddr riscv_calc_kernel_start_addr(RISCVBootInfo *info,\n hwaddr firmware_end_addr) {\n if (info->is_32bit) {\n","prefixes":["v3","02/13"]}