{"id":2225505,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2225505/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260421053140.752059-7-joel@jms.id.au/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260421053140.752059-7-joel@jms.id.au>","list_archive_url":null,"date":"2026-04-21T05:31:31","name":"[v3,06/13] hw/riscv/aia: Provide number of irq sources","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"92f165e84ad24041a06a0044afdd6e7c9fa415ba","submitter":{"id":48628,"url":"http://patchwork.ozlabs.org/api/1.2/people/48628/?format=json","name":"Joel Stanley","email":"joel@jms.id.au"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260421053140.752059-7-joel@jms.id.au/mbox/","series":[{"id":500733,"url":"http://patchwork.ozlabs.org/api/1.2/series/500733/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500733","date":"2026-04-21T05:31:26","name":"hw/riscv: Add the Tenstorrent Atlantis machine","version":3,"mbox":"http://patchwork.ozlabs.org/series/500733/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2225505/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2225505/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=VGBV9R5t;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g0B026HDBz1yCv\n\tfor ; Tue, 21 Apr 2026 15:35:30 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wF3jt-0000Vl-6X; Tue, 21 Apr 2026 01:33:37 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wF3jq-0000V7-VW\n for qemu-devel@nongnu.org; Tue, 21 Apr 2026 01:33:35 -0400","from mail-pj1-x102a.google.com ([2607:f8b0:4864:20::102a])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wF3jp-0004RH-1v\n for qemu-devel@nongnu.org; Tue, 21 Apr 2026 01:33:34 -0400","by mail-pj1-x102a.google.com with SMTP id\n 98e67ed59e1d1-36146ae9dd4so2853503a91.3\n for ; Mon, 20 Apr 2026 22:33:32 -0700 (PDT)","from donnager-debian.. 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This allows other machines to configure this as\nrequired.\n\nThe maximum number of sources is 1023.\n\nReviewed-by: Nutty Liu \nReviewed-by: Daniel Henrique Barboza \nSigned-off-by: Joel Stanley \n---\nv3: Add r-b\n---\n hw/riscv/aia.h | 3 +--\n include/hw/riscv/virt.h | 1 +\n hw/riscv/aia.c | 8 ++++++--\n hw/riscv/virt-acpi-build.c | 25 ++++++++++++++++---------\n hw/riscv/virt.c | 2 ++\n 5 files changed, 26 insertions(+), 13 deletions(-)","diff":"diff --git a/hw/riscv/aia.h b/hw/riscv/aia.h\nindex dbb833340276..5ad0a902be0d 100644\n--- a/hw/riscv/aia.h\n+++ b/hw/riscv/aia.h\n@@ -11,11 +11,10 @@\n \n #include \"exec/hwaddr.h\"\n \n-#define VIRT_IRQCHIP_NUM_SOURCES 96\n-\n uint32_t imsic_num_bits(uint32_t count);\n \n DeviceState *riscv_create_aia(bool msimode, int aia_guests,\n+ uint16_t num_sources,\n const MemMapEntry *aplic_m,\n const MemMapEntry *aplic_s,\n const MemMapEntry *imsic_m,\ndiff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h\nindex ad858deb76ad..36a2def41096 100644\n--- a/include/hw/riscv/virt.h\n+++ b/include/hw/riscv/virt.h\n@@ -64,6 +64,7 @@ struct RISCVVirtState {\n struct GPEXHost *gpex_host;\n OnOffAuto iommu_sys;\n uint16_t pci_iommu_bdf;\n+ uint16_t num_sources;\n };\n \n enum {\ndiff --git a/hw/riscv/aia.c b/hw/riscv/aia.c\nindex c724612a50a5..82ea9d48ea75 100644\n--- a/hw/riscv/aia.c\n+++ b/hw/riscv/aia.c\n@@ -25,6 +25,7 @@ uint32_t imsic_num_bits(uint32_t count)\n }\n \n DeviceState *riscv_create_aia(bool msimode, int aia_guests,\n+ uint16_t num_sources,\n const MemMapEntry *aplic_m,\n const MemMapEntry *aplic_s,\n const MemMapEntry *imsic_m,\n@@ -38,6 +39,9 @@ DeviceState *riscv_create_aia(bool msimode, int aia_guests,\n DeviceState *aplic_s_dev = NULL;\n DeviceState *aplic_m_dev = NULL;\n \n+ /* The RISC-V Advanced Interrupt Architecture, Chapter 1.2. Limits */\n+ g_assert(num_sources <= 1023);\n+\n if (msimode) {\n if (!kvm_enabled()) {\n /* Per-socket M-level IMSICs */\n@@ -66,7 +70,7 @@ DeviceState *riscv_create_aia(bool msimode, int aia_guests,\n aplic_m->size,\n (msimode) ? 0 : base_hartid,\n (msimode) ? 0 : hart_count,\n- VIRT_IRQCHIP_NUM_SOURCES,\n+ num_sources,\n num_prio_bits,\n msimode, true, NULL);\n }\n@@ -77,7 +81,7 @@ DeviceState *riscv_create_aia(bool msimode, int aia_guests,\n aplic_s->size,\n (msimode) ? 0 : base_hartid,\n (msimode) ? 0 : hart_count,\n- VIRT_IRQCHIP_NUM_SOURCES,\n+ num_sources,\n num_prio_bits,\n msimode, false, aplic_m_dev);\n \ndiff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c\nindex 145f8d92ad69..9ef3ef842a28 100644\n--- a/hw/riscv/virt-acpi-build.c\n+++ b/hw/riscv/virt-acpi-build.c\n@@ -146,6 +146,7 @@ static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtState *s)\n }\n \n static void acpi_dsdt_add_plic_aplic(Aml *scope, uint8_t socket_count,\n+ uint16_t num_sources,\n uint64_t mmio_base, uint64_t mmio_size,\n const char *hid)\n {\n@@ -153,9 +154,12 @@ static void acpi_dsdt_add_plic_aplic(Aml *scope, uint8_t socket_count,\n uint32_t gsi_base;\n uint8_t socket;\n \n+ /* The RISC-V Advanced Interrupt Architecture, Chapter 1.2. Limits */\n+ g_assert(num_sources <= 1023);\n+\n for (socket = 0; socket < socket_count; socket++) {\n plic_aplic_addr = mmio_base + mmio_size * socket;\n- gsi_base = VIRT_IRQCHIP_NUM_SOURCES * socket;\n+ gsi_base = num_sources * socket;\n Aml *dev = aml_device(\"IC%.02X\", socket);\n aml_append(dev, aml_name_decl(\"_HID\", aml_string(\"%s\", hid)));\n aml_append(dev, aml_name_decl(\"_UID\", aml_int(socket)));\n@@ -474,10 +478,13 @@ static void build_dsdt(GArray *table_data,\n socket_count = riscv_socket_count(ms);\n \n if (s->aia_type == VIRT_AIA_TYPE_NONE) {\n- acpi_dsdt_add_plic_aplic(scope, socket_count, memmap[VIRT_PLIC].base,\n- memmap[VIRT_PLIC].size, \"RSCV0001\");\n+ acpi_dsdt_add_plic_aplic(scope, socket_count, s->num_sources,\n+ memmap[VIRT_PLIC].base,\n+ memmap[VIRT_PLIC].size,\n+ \"RSCV0001\");\n } else {\n- acpi_dsdt_add_plic_aplic(scope, socket_count, memmap[VIRT_APLIC_S].base,\n+ acpi_dsdt_add_plic_aplic(scope, socket_count, s->num_sources,\n+ memmap[VIRT_APLIC_S].base,\n memmap[VIRT_APLIC_S].size, \"RSCV0002\");\n }\n \n@@ -494,15 +501,15 @@ static void build_dsdt(GArray *table_data,\n } else if (socket_count == 2) {\n virtio_acpi_dsdt_add(scope, memmap[VIRT_VIRTIO].base,\n memmap[VIRT_VIRTIO].size,\n- VIRTIO_IRQ + VIRT_IRQCHIP_NUM_SOURCES, 0,\n+ VIRTIO_IRQ + s->num_sources, 0,\n VIRTIO_COUNT);\n- acpi_dsdt_add_gpex_host(scope, PCIE_IRQ + VIRT_IRQCHIP_NUM_SOURCES);\n+ acpi_dsdt_add_gpex_host(scope, PCIE_IRQ + s->num_sources);\n } else {\n virtio_acpi_dsdt_add(scope, memmap[VIRT_VIRTIO].base,\n memmap[VIRT_VIRTIO].size,\n- VIRTIO_IRQ + VIRT_IRQCHIP_NUM_SOURCES, 0,\n+ VIRTIO_IRQ + s->num_sources, 0,\n VIRTIO_COUNT);\n- acpi_dsdt_add_gpex_host(scope, PCIE_IRQ + VIRT_IRQCHIP_NUM_SOURCES * 2);\n+ acpi_dsdt_add_gpex_host(scope, PCIE_IRQ + s->num_sources * 2);\n }\n \n aml_append(dsdt, scope);\n@@ -581,7 +588,7 @@ static void build_madt(GArray *table_data,\n for (socket = 0; socket < riscv_socket_count(ms); socket++) {\n aplic_addr = s->memmap[VIRT_APLIC_S].base +\n s->memmap[VIRT_APLIC_S].size * socket;\n- gsi_base = VIRT_IRQCHIP_NUM_SOURCES * socket;\n+ gsi_base = s->num_sources * socket;\n build_append_int_noprefix(table_data, 0x1A, 1); /* Type */\n build_append_int_noprefix(table_data, 36, 1); /* Length */\n build_append_int_noprefix(table_data, 1, 1); /* Version */\ndiff --git a/hw/riscv/virt.c b/hw/riscv/virt.c\nindex ce0fd6f50c4a..6c5bcd43dc54 100644\n--- a/hw/riscv/virt.c\n+++ b/hw/riscv/virt.c\n@@ -1548,6 +1548,7 @@ static void virt_machine_init(MachineState *machine)\n } else {\n s->irqchip[i] = riscv_create_aia(s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC,\n s->aia_guests,\n+ s->num_sources,\n &s->memmap[VIRT_APLIC_M],\n &s->memmap[VIRT_APLIC_S],\n &s->memmap[VIRT_IMSIC_M],\n@@ -1691,6 +1692,7 @@ static void virt_machine_instance_init(Object *obj)\n s->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8);\n s->acpi = ON_OFF_AUTO_AUTO;\n s->iommu_sys = ON_OFF_AUTO_AUTO;\n+ s->num_sources = VIRT_IRQCHIP_NUM_SOURCES;\n }\n \n static char *virt_get_aia_guests(Object *obj, Error **errp)\n","prefixes":["v3","06/13"]}