{"id":2225493,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2225493/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260421-mshv_accel_arm64_supp-v3-11-469f544778ba@linux.microsoft.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260421-mshv_accel_arm64_supp-v3-11-469f544778ba@linux.microsoft.com>","list_archive_url":null,"date":"2026-04-21T05:21:56","name":"[v3,11/14] target/arm/mshv: add vCPU run loop","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"f701d0df513aeed5097b159505ad300c2b2ce7f0","submitter":{"id":92925,"url":"http://patchwork.ozlabs.org/api/1.2/people/92925/?format=json","name":"Aastha Rawat","email":"aastharawat@linux.microsoft.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260421-mshv_accel_arm64_supp-v3-11-469f544778ba@linux.microsoft.com/mbox/","series":[{"id":500731,"url":"http://patchwork.ozlabs.org/api/1.2/series/500731/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500731","date":"2026-04-21T05:21:47","name":"Add ARM64 support for MSHV accelerator","version":3,"mbox":"http://patchwork.ozlabs.org/series/500731/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2225493/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2225493/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=linux.microsoft.com header.i=@linux.microsoft.com\n header.a=rsa-sha256 header.s=default header.b=PCwaIM+P;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com;\n s=default; t=1776748921;\n bh=fA+A7bqtE3RxxEmcOmCmzIZRD5MNzhA6TFdYbdUgxsE=;\n h=From:Date:Subject:References:In-Reply-To:To:Cc:From;\n b=PCwaIM+P7i1n4BZsF2HQfmvMiq3eFZiu4Ldh6AlZ4U0/bxsDd0jh+7/YLXVkWlHNa\n OKcZIGt+SHeAnroRp2N1B8435dJRRJPMSFBap87TOw+d6D7jOORxeHu1NyIusgMt6i\n iqAHjKlK8QJ/53Hbbg/Wp4VHC9OabprA+mNYrUG0=","From":"Aastha Rawat ","Date":"Tue, 21 Apr 2026 05:21:56 +0000","Subject":"[PATCH v3 11/14] target/arm/mshv: add vCPU run loop","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"7bit","Message-Id":"\n <20260421-mshv_accel_arm64_supp-v3-11-469f544778ba@linux.microsoft.com>","References":"\n <20260421-mshv_accel_arm64_supp-v3-0-469f544778ba@linux.microsoft.com>","In-Reply-To":"\n <20260421-mshv_accel_arm64_supp-v3-0-469f544778ba@linux.microsoft.com>","To":"qemu-devel@nongnu.org","Cc":"Magnus Kulke ,\n Wei Liu , Paolo Bonzini ,\n\t=?utf-8?q?Marc-Andr=C3=A9_Lureau?= ,\n\t=?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , =?utf-8?q?Phil?=\n\t=?utf-8?q?ippe_Mathieu-Daud=C3=A9?= ,\n Peter Maydell ,\n Anirudh Rayabharam ,\n Aastha Rawat ,\n Magnus Kulke , qemu-arm@nongnu.org,\n Alexander Graf , Pedro Barbuda ,\n Mohamed Mediouni ","X-Mailer":"b4 0.15.1","Received-SPF":"pass client-ip=13.77.154.182;\n envelope-from=aastharawat@linux.microsoft.com; helo=linux.microsoft.com","X-Spam_score_int":"-42","X-Spam_score":"-4.3","X-Spam_bar":"----","X-Spam_report":"(-4.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, RCVD_IN_DNSWL_MED=-2.3,\n SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: \"Anirudh Rayabharam (Microsoft)\" \n\nAdd the main vCPU run loop for MSHV using the MSHV_RUN_VP_IOCTL.\n\nHandle MMIO exits by emulating the instruction using the syndrome\ninformation from ESR_EL2.\n\nSigned-off-by: Anirudh Rayabharam (Microsoft) \n---\n include/hw/hyperv/hvgdk_mini.h | 44 +++++++++++++++++++\n target/arm/mshv/mshv-all.c | 96 ++++++++++++++++++++++++++++++++++++++++++\n 2 files changed, 140 insertions(+)","diff":"diff --git a/include/hw/hyperv/hvgdk_mini.h b/include/hw/hyperv/hvgdk_mini.h\nindex d56be0d70f..84b3c6af5f 100644\n--- a/include/hw/hyperv/hvgdk_mini.h\n+++ b/include/hw/hyperv/hvgdk_mini.h\n@@ -750,6 +750,50 @@ struct hv_x64_memory_intercept_message {\n uint8_t instruction_bytes[16];\n };\n \n+union hv_arm64_vp_execution_state {\n+ uint16_t as_uint16;\n+ struct {\n+ uint16_t cpl:2;\n+ uint16_t debug_active:1;\n+ uint16_t interruption_pending:1;\n+ uint16_t vtl:4;\n+ uint16_t virtualization_fault_active:1;\n+ uint16_t reserved:7;\n+ };\n+};\n+\n+struct hv_arm64_intercept_message_header {\n+ uint32_t vp_index;\n+ uint8_t instruction_length;\n+ uint8_t intercept_access_type;\n+ union hv_arm64_vp_execution_state execution_state;\n+ uint64_t pc;\n+ uint64_t cpsr;\n+};\n+\n+union hv_arm64_memory_access_info {\n+ uint8_t as_uint8;\n+ struct {\n+ uint8_t gva_valid:1;\n+ uint8_t gva_gpa_valid:1;\n+ uint8_t hypercall_output_pending:1;\n+ uint8_t reserved:5;\n+ };\n+};\n+\n+struct hv_arm64_memory_intercept_message {\n+ struct hv_arm64_intercept_message_header header;\n+ uint32_t cache_type; /* enum hv_cache_type */\n+ uint8_t instruction_byte_count;\n+ union hv_arm64_memory_access_info memory_access_info;\n+ uint16_t reserved1;\n+ uint8_t instruction_bytes[4];\n+ uint32_t reserved2;\n+ uint64_t guest_virtual_address;\n+ uint64_t guest_physical_address;\n+ uint64_t syndrome;\n+};\n+\n union hv_message_flags {\n uint8_t asu8;\n struct {\ndiff --git a/target/arm/mshv/mshv-all.c b/target/arm/mshv/mshv-all.c\nindex 8d16971c0d..a2d07bec12 100644\n--- a/target/arm/mshv/mshv-all.c\n+++ b/target/arm/mshv/mshv-all.c\n@@ -21,6 +21,7 @@\n #include \"target/arm/cpu.h\"\n #include \"target/arm/internals.h\"\n #include \"target/arm/mshv_arm.h\"\n+#include \"target/arm/helper.h\"\n \n #include \"system/mshv.h\"\n #include \"system/mshv_int.h\"\n@@ -166,8 +167,103 @@ int mshv_arch_put_registers(const CPUState *cpu)\n return 0;\n }\n \n+static int set_memory_info(const struct hyperv_message *msg,\n+ struct hv_arm64_memory_intercept_message *info)\n+{\n+ if (msg->header.message_type != HVMSG_GPA_INTERCEPT\n+ && msg->header.message_type != HVMSG_UNMAPPED_GPA\n+ && msg->header.message_type != HVMSG_UNACCEPTED_GPA) {\n+ error_report(\"invalid message type\");\n+ return -1;\n+ }\n+ memcpy(info, msg->payload, sizeof(*info));\n+\n+ return 0;\n+}\n+\n+int mshv_store_regs(CPUState *cpu)\n+{\n+ int ret;\n+\n+ ret = set_standard_regs(cpu);\n+ if (ret < 0) {\n+ error_report(\"Failed to store standard registers\");\n+ return -1;\n+ }\n+\n+ return 0;\n+}\n+\n+static int handle_unmapped_mem(int vm_fd, CPUState *cpu,\n+ const struct hyperv_message *msg,\n+ MshvVmExit *exit_reason)\n+{\n+ struct hv_arm64_memory_intercept_message info = { 0 };\n+ ARMCPU *arm_cpu = ARM_CPU(cpu);\n+ CPUARMState *env = &arm_cpu->env;\n+ int ret;\n+ EsrEl2 syndrome;\n+\n+ ret = set_memory_info(msg, &info);\n+ if (ret < 0) {\n+ error_report(\"failed to convert message to memory info\");\n+ return -1;\n+ }\n+\n+ syndrome.raw = info.syndrome;\n+\n+ ret = mshv_load_regs(cpu);\n+ if (ret < 0) {\n+ error_report(\"Failed to load registers\");\n+ return -1;\n+ }\n+\n+ ret = arm_emulate_mmio(cpu, syndrome, info.guest_physical_address);\n+ if (ret < 0) {\n+ error_report(\"Failed to emulate with syndrome\");\n+ return -1;\n+ }\n+\n+ env->pc += (syndrome.il == 1) ? 4 : 2;\n+\n+ ret = mshv_store_regs(cpu);\n+ if (ret < 0) {\n+ error_report(\"Failed to store registers\");\n+ return -1;\n+ }\n+ *exit_reason = MshvVmExitIgnore;\n+\n+ return 0;\n+}\n+\n int mshv_run_vcpu(int vm_fd, CPUState *cpu, hv_message *msg, MshvVmExit *exit)\n {\n+ int ret;\n+ int cpu_fd = mshv_vcpufd(cpu);\n+\n+ ret = ioctl(cpu_fd, MSHV_RUN_VP, msg);\n+ if (ret < 0) {\n+ *exit = MshvVmExitShutdown;\n+ return ret;\n+ }\n+\n+ switch (msg->header.message_type) {\n+ case HVMSG_UNRECOVERABLE_EXCEPTION:\n+ *exit = MshvVmExitShutdown;\n+ break;\n+ case HVMSG_GPA_INTERCEPT:\n+ case HVMSG_UNMAPPED_GPA:\n+ ret = handle_unmapped_mem(vm_fd, cpu, msg, exit);\n+ if (ret < 0) {\n+ error_report(\"failed to handle mmio\");\n+ return -1;\n+ }\n+ break;\n+ default:\n+ error_report(\"Unhandled message type: 0x%x\", msg->header.message_type);\n+ return -1;\n+ }\n+\n return 0;\n }\n \n","prefixes":["v3","11/14"]}