{"id":2225456,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2225456/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260421051346.41106-9-richard.henderson@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260421051346.41106-9-richard.henderson@linaro.org>","list_archive_url":null,"date":"2026-04-21T05:13:17","name":"[08/37] target/arm: Introduce FPMR","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"2cc6533c169c1b1f36aa58549a030c72eb0f9cc8","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/1.2/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260421051346.41106-9-richard.henderson@linaro.org/mbox/","series":[{"id":500729,"url":"http://patchwork.ozlabs.org/api/1.2/series/500729/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500729","date":"2026-04-21T05:13:11","name":"target/arm: Implement FEAT_FAMINMAX, FEAT_FPMR, FEAT_FP8","version":1,"mbox":"http://patchwork.ozlabs.org/series/500729/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2225456/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2225456/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=xWB4/M8B;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g09c71JYYz1yJG\n\tfor ; Tue, 21 Apr 2026 15:18:15 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wF3Ru-0008F4-TU; Tue, 21 Apr 2026 01:15:03 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wF3RC-0007xh-V2\n for qemu-devel@nongnu.org; Tue, 21 Apr 2026 01:14:24 -0400","from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wF3R8-0006MT-UJ\n for qemu-devel@nongnu.org; Tue, 21 Apr 2026 01:14:18 -0400","by mail-pl1-x62a.google.com with SMTP id\n d9443c01a7336-2a8fba3f769so16746995ad.2\n for ; Mon, 20 Apr 2026 22:14:12 -0700 (PDT)","from stoup.. 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","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Introduce the special register FPMR and its fields.\nMigrate it when present.\n\nSigned-off-by: Richard Henderson \n---\n target/arm/cpregs.h | 5 +++++\n target/arm/cpu-features.h | 5 +++++\n target/arm/cpu.h | 1 +\n target/arm/internals.h | 9 +++++++++\n target/arm/helper.c | 12 +++++++++++-\n target/arm/machine.c | 20 ++++++++++++++++++++\n 6 files changed, 51 insertions(+), 1 deletion(-)","diff":"diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h\nindex f5ec7484c1..391c0e322b 100644\n--- a/target/arm/cpregs.h\n+++ b/target/arm/cpregs.h\n@@ -149,6 +149,11 @@ enum {\n * should not trap to EL2 when HCR_EL2.NV is set.\n */\n ARM_CP_NV_NO_TRAP = 1 << 22,\n+ /*\n+ * Flag: Access check for this sysreg is constrained by the\n+ * ARM pseudocode function CheckFPMREnabled().\n+ */\n+ ARM_CP_FPMR = 1 << 23,\n };\n \n /*\ndiff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h\nindex 03631018d7..ddef6fbeb0 100644\n--- a/target/arm/cpu-features.h\n+++ b/target/arm/cpu-features.h\n@@ -1173,6 +1173,11 @@ static inline bool isar_feature_aa64_gcs(const ARMISARegisters *id)\n return FIELD_EX64_IDREG(id, ID_AA64PFR1, GCS) != 0;\n }\n \n+static inline bool isar_feature_aa64_fpmr(const ARMISARegisters *id)\n+{\n+ return FIELD_EX64_IDREG(id, ID_AA64PFR2, FPMR) != 0;\n+}\n+\n static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id)\n {\n return FIELD_SEX64_IDREG(id, ID_AA64MMFR0, TGRAN4) >= 1;\ndiff --git a/target/arm/cpu.h b/target/arm/cpu.h\nindex 6ec3845edf..38deea01bc 100644\n--- a/target/arm/cpu.h\n+++ b/target/arm/cpu.h\n@@ -692,6 +692,7 @@ typedef struct CPUArchState {\n */\n uint64_t fpsr;\n uint64_t fpcr;\n+ uint64_t fpmr;\n \n uint32_t xregs[16];\n \ndiff --git a/target/arm/internals.h b/target/arm/internals.h\nindex b0f6bfa62c..944adc14e7 100644\n--- a/target/arm/internals.h\n+++ b/target/arm/internals.h\n@@ -286,6 +286,15 @@ FIELD(CNTHCTL, EVNTIS, 17, 1)\n FIELD(CNTHCTL, CNTVMASK, 18, 1)\n FIELD(CNTHCTL, CNTPMASK, 19, 1)\n \n+FIELD(FPMR, F8S1, 0, 3)\n+FIELD(FPMR, F8S2, 3, 3)\n+FIELD(FPMR, F8D, 6, 3)\n+FIELD(FPMR, OSM, 14, 1)\n+FIELD(FPMR, OSC, 15, 1)\n+FIELD(FPMR, LSCALE, 16, 7)\n+FIELD(FPMR, NSCALE, 24, 8)\n+FIELD(FPMR, LSCALE2, 32, 6)\n+\n /* We use a few fake FSR values for internal purposes in M profile.\n * M profile cores don't have A/R format FSRs, but currently our\n * get_phys_addr() code assumes A/R profile and reports failures via\ndiff --git a/target/arm/helper.c b/target/arm/helper.c\nindex 08285b69a7..1a0673a343 100644\n--- a/target/arm/helper.c\n+++ b/target/arm/helper.c\n@@ -6286,6 +6286,14 @@ static const ARMCPRegInfo aie_reginfo[] = {\n .type = ARM_CP_CONST, .resetvalue = 0 },\n };\n \n+static const ARMCPRegInfo fpmr_reginfo[] = {\n+ { .name = \"FPMR\", .state = ARM_CP_STATE_AA64,\n+ .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 4, .opc2 = 2,\n+ .access = PL0_RW, .type = ARM_CP_FPU | ARM_CP_FPMR,\n+ .fieldoffset = offsetof(CPUARMState, vfp.fpmr),\n+ }\n+};\n+\n void register_cp_regs_for_features(ARMCPU *cpu)\n {\n /* Register all the coprocessor registers based on feature bits */\n@@ -7535,10 +7543,12 @@ void register_cp_regs_for_features(ARMCPU *cpu)\n define_arm_cp_regs(cpu, mec_mte_reginfo);\n }\n }\n-\n if (cpu_isar_feature(aa64_aie, cpu)) {\n define_arm_cp_regs(cpu, aie_reginfo);\n }\n+ if (cpu_isar_feature(aa64_fpmr, cpu)) {\n+ define_arm_cp_regs(cpu, fpmr_reginfo);\n+ }\n \n if (cpu_isar_feature(any_predinv, cpu)) {\n define_arm_cp_regs(cpu, predinv_reginfo);\ndiff --git a/target/arm/machine.c b/target/arm/machine.c\nindex b0e499515c..11e973e504 100644\n--- a/target/arm/machine.c\n+++ b/target/arm/machine.c\n@@ -960,6 +960,25 @@ static const VMStateDescription vmstate_syndrome64 = {\n },\n };\n \n+static bool fpmr_needed(void *opaque)\n+{\n+ ARMCPU *cpu = opaque;\n+\n+ return arm_feature(&cpu->env, ARM_FEATURE_AARCH64)\n+ && cpu_isar_feature(aa64_fpmr, cpu);\n+}\n+\n+static const VMStateDescription vmstate_fpmr = {\n+ .name = \"cpu/fpmr\",\n+ .version_id = 1,\n+ .minimum_version_id = 1,\n+ .needed = fpmr_needed,\n+ .fields = (const VMStateField[]) {\n+ VMSTATE_UINT64(env.vfp.fpmr, ARMCPU),\n+ VMSTATE_END_OF_LIST()\n+ },\n+};\n+\n static int cpu_pre_save(void *opaque)\n {\n ARMCPU *cpu = opaque;\n@@ -1310,6 +1329,7 @@ const VMStateDescription vmstate_arm_cpu = {\n &vmstate_syndrome64,\n &vmstate_pstate64,\n &vmstate_event,\n+ &vmstate_fpmr,\n NULL\n }\n };\n","prefixes":["08/37"]}