{"id":2224659,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2224659/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417173105.1648172-12-peter.maydell@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260417173105.1648172-12-peter.maydell@linaro.org>","list_archive_url":null,"date":"2026-04-17T17:30:59","name":"[11/17] target/arm: Rename arm_cpu_get_phys_page()","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"4fe429424f45841fc7deb36c6fd8921373c4cbff","submitter":{"id":5111,"url":"http://patchwork.ozlabs.org/api/1.2/people/5111/?format=json","name":"Peter Maydell","email":"peter.maydell@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417173105.1648172-12-peter.maydell@linaro.org/mbox/","series":[{"id":500380,"url":"http://patchwork.ozlabs.org/api/1.2/series/500380/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500380","date":"2026-04-17T17:30:51","name":"Handle sub-page granularity in cpu_memory_rw_debug()","version":1,"mbox":"http://patchwork.ozlabs.org/series/500380/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2224659/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2224659/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=nXm9Ixy0;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fy29b0RFVz1yD3\n\tfor ; Sat, 18 Apr 2026 03:36:19 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wDn35-0007N5-Oi; Fri, 17 Apr 2026 13:32:11 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wDn2Y-0006pu-Ql\n for qemu-devel@nongnu.org; Fri, 17 Apr 2026 13:31:42 -0400","from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wDn2S-0002Ad-Uq\n for qemu-devel@nongnu.org; Fri, 17 Apr 2026 13:31:38 -0400","by mail-wr1-x42b.google.com with SMTP id\n ffacd0b85a97d-43eada6d900so875762f8f.0\n for ; Fri, 17 Apr 2026 10:31:32 -0700 (PDT)","from lanath.. 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Iglesias\" ,\n Jiaxun Yang , Nicholas Piggin ,\n Chinmay Rath , Glenn Miles ,\n Palmer Dabbelt ,\n Alistair Francis , Weiwei Li ,\n Daniel Henrique Barboza ,\n Liu Zhiwei ,\n Chao Liu , Ilya Leoshkevich ,\n David Hildenbrand ,\n Mark Cave-Ayland ,\n Artyom Tarasenko ","Subject":"[PATCH 11/17] target/arm: Rename arm_cpu_get_phys_page()","Date":"Fri, 17 Apr 2026 18:30:59 +0100","Message-ID":"<20260417173105.1648172-12-peter.maydell@linaro.org>","X-Mailer":"git-send-email 2.43.0","In-Reply-To":"<20260417173105.1648172-1-peter.maydell@linaro.org>","References":"<20260417173105.1648172-1-peter.maydell@linaro.org>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2a00:1450:4864:20::42b;\n envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"The internal helper function arm_cpu_get_phys_page() is named that\nway because of its use in the get_phys_page_attrs_debug method. Now\nwe've renamed the method, rename the helper to match, since it can\nhandle non-page-aligned addresses.\n\nSigned-off-by: Peter Maydell \n---\n target/arm/ptw.c | 8 ++++----\n 1 file changed, 4 insertions(+), 4 deletions(-)","diff":"diff --git a/target/arm/ptw.c b/target/arm/ptw.c\nindex f5f624c7c3..8be6f243e6 100644\n--- a/target/arm/ptw.c\n+++ b/target/arm/ptw.c\n@@ -3922,7 +3922,7 @@ bool get_phys_addr(CPUARMState *env, vaddr address,\n memop, result, fi);\n }\n \n-static hwaddr arm_cpu_get_phys_page(CPUARMState *env, vaddr addr,\n+static hwaddr arm_cpu_get_phys_addr(CPUARMState *env, vaddr addr,\n MemTxAttrs *attrs, ARMMMUIdx mmu_idx)\n {\n S1Translate ptw = {\n@@ -3950,7 +3950,7 @@ hwaddr arm_cpu_get_phys_addr_attrs_debug(CPUState *cs, vaddr addr,\n CPUARMState *env = &cpu->env;\n ARMMMUIdx mmu_idx = arm_mmu_idx(env);\n \n- hwaddr res = arm_cpu_get_phys_page(env, addr, attrs, mmu_idx);\n+ hwaddr res = arm_cpu_get_phys_addr(env, addr, attrs, mmu_idx);\n \n if (res != -1) {\n return res;\n@@ -3964,10 +3964,10 @@ hwaddr arm_cpu_get_phys_addr_attrs_debug(CPUState *cs, vaddr addr,\n switch (mmu_idx) {\n case ARMMMUIdx_E10_1:\n case ARMMMUIdx_E10_1_PAN:\n- return arm_cpu_get_phys_page(env, addr, attrs, ARMMMUIdx_E10_0);\n+ return arm_cpu_get_phys_addr(env, addr, attrs, ARMMMUIdx_E10_0);\n case ARMMMUIdx_E20_2:\n case ARMMMUIdx_E20_2_PAN:\n- return arm_cpu_get_phys_page(env, addr, attrs, ARMMMUIdx_E20_0);\n+ return arm_cpu_get_phys_addr(env, addr, attrs, ARMMMUIdx_E20_0);\n default:\n return -1;\n }\n","prefixes":["11/17"]}