{"id":2224645,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2224645/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417173105.1648172-9-peter.maydell@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260417173105.1648172-9-peter.maydell@linaro.org>","list_archive_url":null,"date":"2026-04-17T17:30:56","name":"[08/17] target: Rename get_phys_page_debug to get_phys_addr_debug","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"53ca935c34142789c7417c75bc5aff66f2fbf6cf","submitter":{"id":5111,"url":"http://patchwork.ozlabs.org/api/1.2/people/5111/?format=json","name":"Peter Maydell","email":"peter.maydell@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417173105.1648172-9-peter.maydell@linaro.org/mbox/","series":[{"id":500380,"url":"http://patchwork.ozlabs.org/api/1.2/series/500380/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500380","date":"2026-04-17T17:30:51","name":"Handle sub-page granularity in cpu_memory_rw_debug()","version":1,"mbox":"http://patchwork.ozlabs.org/series/500380/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2224645/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2224645/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=KIzj5pyb;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fy28R6pdQz1yD3\n\tfor ; Sat, 18 Apr 2026 03:35:19 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wDn36-0007Ot-Ut; Fri, 17 Apr 2026 13:32:12 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wDn2X-0006pb-IZ\n for qemu-devel@nongnu.org; Fri, 17 Apr 2026 13:31:42 -0400","from mail-wr1-x434.google.com ([2a00:1450:4864:20::434])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wDn2O-00026F-Pb\n for qemu-devel@nongnu.org; Fri, 17 Apr 2026 13:31:35 -0400","by mail-wr1-x434.google.com with SMTP id\n ffacd0b85a97d-43fe608cb92so560097f8f.2\n for ; Fri, 17 Apr 2026 10:31:27 -0700 (PDT)","from lanath.. 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Iglesias\" ,\n Jiaxun Yang , Nicholas Piggin ,\n Chinmay Rath , Glenn Miles ,\n Palmer Dabbelt ,\n Alistair Francis , Weiwei Li ,\n Daniel Henrique Barboza ,\n Liu Zhiwei ,\n Chao Liu , Ilya Leoshkevich ,\n David Hildenbrand ,\n Mark Cave-Ayland ,\n Artyom Tarasenko ","Subject":"[PATCH 08/17] target: Rename get_phys_page_debug to\n get_phys_addr_debug","Date":"Fri, 17 Apr 2026 18:30:56 +0100","Message-ID":"<20260417173105.1648172-9-peter.maydell@linaro.org>","X-Mailer":"git-send-email 2.43.0","In-Reply-To":"<20260417173105.1648172-1-peter.maydell@linaro.org>","References":"<20260417173105.1648172-1-peter.maydell@linaro.org>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2a00:1450:4864:20::434;\n envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Now that we have ensured that all implementations of the get_phys_page_debug\nmethod handle a non-page-aligned input and return the corresponding\nnon-page-aligned output, the name of the method is somewhat misleading.\nRename it to get_phys_addr_debug.\n\nThis commit was produced with the commands\n\n sed -i -e 's/_cpu_get_phys_page_debug/_cpu_get_phys_addr_debug/g;s/\\/get_phys_addr_debug/g' $(git grep -l get_phys_page_debug)\n sed -i -e 's/_cpu_get_phys_page_attrs_debug/_cpu_get_phys_addr_attrs_debug/g;s/\\/get_phys_addr_attrs_debug/g' $(git grep -l get_phys_page_attrs_debug)\n\nwhich catches all references to the method name itself plus\nthe functions which each target uses as the method implementation,\nbut (deliberately) not the cpu_phys_get_page_debug() and\ncpu_phys_get_page_attrs_debug() wrapper functions or their callers.\n(We'll deal with those in the next commit.)\n\nSigned-off-by: Peter Maydell \n---\n hw/core/cpu-system.c | 6 +++---\n include/hw/core/sysemu-cpu-ops.h | 10 +++++-----\n target/alpha/cpu.c | 2 +-\n target/alpha/cpu.h | 2 +-\n target/alpha/helper.c | 2 +-\n target/arm/cpu.c | 2 +-\n target/arm/cpu.h | 2 +-\n target/arm/ptw.c | 2 +-\n target/avr/cpu.c | 2 +-\n target/avr/cpu.h | 2 +-\n target/avr/helper.c | 2 +-\n target/hppa/cpu.c | 2 +-\n target/hppa/cpu.h | 2 +-\n target/hppa/mem_helper.c | 2 +-\n target/i386/cpu.c | 2 +-\n target/i386/cpu.h | 2 +-\n target/i386/helper.c | 2 +-\n target/i386/whpx/whpx-all.c | 2 +-\n target/loongarch/cpu-mmu.h | 2 +-\n target/loongarch/cpu.c | 2 +-\n target/loongarch/cpu_helper.c | 2 +-\n target/m68k/cpu.c | 2 +-\n target/m68k/cpu.h | 2 +-\n target/m68k/helper.c | 2 +-\n target/microblaze/cpu.c | 2 +-\n target/microblaze/cpu.h | 2 +-\n target/microblaze/helper.c | 2 +-\n target/mips/cpu.c | 2 +-\n target/mips/internal.h | 2 +-\n target/mips/system/physaddr.c | 2 +-\n target/or1k/cpu.c | 2 +-\n target/or1k/cpu.h | 2 +-\n target/or1k/mmu.c | 2 +-\n target/ppc/cpu.h | 2 +-\n target/ppc/cpu_init.c | 2 +-\n target/ppc/mmu-hash32.c | 2 +-\n target/ppc/mmu_common.c | 2 +-\n target/riscv/cpu.c | 2 +-\n target/riscv/cpu.h | 2 +-\n target/riscv/cpu_helper.c | 2 +-\n target/rx/cpu.c | 2 +-\n target/rx/cpu.h | 2 +-\n target/rx/helper.c | 2 +-\n target/s390x/cpu-system.c | 2 +-\n target/sh4/cpu.c | 2 +-\n target/sh4/cpu.h | 2 +-\n target/sh4/helper.c | 2 +-\n target/sparc/cpu.c | 2 +-\n target/sparc/cpu.h | 2 +-\n target/sparc/mmu_helper.c | 2 +-\n target/tricore/cpu.c | 2 +-\n target/tricore/cpu.h | 2 +-\n target/tricore/helper.c | 2 +-\n target/xtensa/cpu.c | 2 +-\n target/xtensa/cpu.h | 2 +-\n target/xtensa/mmu_helper.c | 2 +-\n 56 files changed, 62 insertions(+), 62 deletions(-)","diff":"diff --git a/hw/core/cpu-system.c b/hw/core/cpu-system.c\nindex 273b9b7c22..93dc861083 100644\n--- a/hw/core/cpu-system.c\n+++ b/hw/core/cpu-system.c\n@@ -60,13 +60,13 @@ hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,\n {\n hwaddr paddr;\n \n- if (cpu->cc->sysemu_ops->get_phys_page_attrs_debug) {\n- paddr = cpu->cc->sysemu_ops->get_phys_page_attrs_debug(cpu, addr,\n+ if (cpu->cc->sysemu_ops->get_phys_addr_attrs_debug) {\n+ paddr = cpu->cc->sysemu_ops->get_phys_addr_attrs_debug(cpu, addr,\n attrs);\n } else {\n /* Fallback for CPUs which don't implement the _attrs_ hook */\n *attrs = MEMTXATTRS_UNSPECIFIED;\n- paddr = cpu->cc->sysemu_ops->get_phys_page_debug(cpu, addr);\n+ paddr = cpu->cc->sysemu_ops->get_phys_addr_debug(cpu, addr);\n }\n /* Indicate that this is a debug access. */\n attrs->debug = 1;\ndiff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h\nindex 7b2d2d2610..a4fc330bea 100644\n--- a/include/hw/core/sysemu-cpu-ops.h\n+++ b/include/hw/core/sysemu-cpu-ops.h\n@@ -30,17 +30,17 @@ typedef struct SysemuCPUOps {\n */\n bool (*get_paging_enabled)(const CPUState *cpu);\n /**\n- * @get_phys_page_debug: Callback for obtaining a physical address.\n+ * @get_phys_addr_debug: Callback for obtaining a physical address.\n */\n- hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr);\n+ hwaddr (*get_phys_addr_debug)(CPUState *cpu, vaddr addr);\n /**\n- * @get_phys_page_attrs_debug: Callback for obtaining a physical address\n+ * @get_phys_addr_attrs_debug: Callback for obtaining a physical address\n * and the associated memory transaction attributes to use for the\n * access.\n * CPUs which use memory transaction attributes should implement this\n- * instead of get_phys_page_debug.\n+ * instead of get_phys_addr_debug.\n */\n- hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr,\n+ hwaddr (*get_phys_addr_attrs_debug)(CPUState *cpu, vaddr addr,\n MemTxAttrs *attrs);\n /**\n * @asidx_from_attrs: Callback to return the CPU AddressSpace to use for\ndiff --git a/target/alpha/cpu.c b/target/alpha/cpu.c\nindex ff053043a3..0c35067b20 100644\n--- a/target/alpha/cpu.c\n+++ b/target/alpha/cpu.c\n@@ -242,7 +242,7 @@ static void alpha_cpu_initfn(Object *obj)\n \n static const struct SysemuCPUOps alpha_sysemu_ops = {\n .has_work = alpha_cpu_has_work,\n- .get_phys_page_debug = alpha_cpu_get_phys_page_debug,\n+ .get_phys_addr_debug = alpha_cpu_get_phys_addr_debug,\n };\n #endif\n \ndiff --git a/target/alpha/cpu.h b/target/alpha/cpu.h\nindex 45944e46b5..e49ebca578 100644\n--- a/target/alpha/cpu.h\n+++ b/target/alpha/cpu.h\n@@ -283,7 +283,7 @@ extern const VMStateDescription vmstate_alpha_cpu;\n \n void alpha_cpu_do_interrupt(CPUState *cpu);\n bool alpha_cpu_exec_interrupt(CPUState *cpu, int int_req);\n-hwaddr alpha_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);\n+hwaddr alpha_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr);\n #endif /* !CONFIG_USER_ONLY */\n void alpha_cpu_dump_state(CPUState *cs, FILE *f, int flags);\n int alpha_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);\ndiff --git a/target/alpha/helper.c b/target/alpha/helper.c\nindex af6d7847d5..33fed0c746 100644\n--- a/target/alpha/helper.c\n+++ b/target/alpha/helper.c\n@@ -295,7 +295,7 @@ static int get_physical_address(CPUAlphaState *env, vaddr addr,\n return ret;\n }\n \n-hwaddr alpha_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)\n+hwaddr alpha_cpu_get_phys_addr_debug(CPUState *cs, vaddr addr)\n {\n hwaddr phys;\n int prot, fail;\ndiff --git a/target/arm/cpu.c b/target/arm/cpu.c\nindex ccc47c8a9a..f28c74a94b 100644\n--- a/target/arm/cpu.c\n+++ b/target/arm/cpu.c\n@@ -2295,7 +2295,7 @@ static vaddr aarch64_untagged_addr(CPUState *cs, vaddr x)\n \n static const struct SysemuCPUOps arm_sysemu_ops = {\n .has_work = arm_cpu_has_work,\n- .get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug,\n+ .get_phys_addr_attrs_debug = arm_cpu_get_phys_addr_attrs_debug,\n .asidx_from_attrs = arm_asidx_from_attrs,\n .write_elf32_note = arm_cpu_write_elf32_note,\n .write_elf64_note = arm_cpu_write_elf64_note,\ndiff --git a/target/arm/cpu.h b/target/arm/cpu.h\nindex 657ff4ab20..917e4668da 100644\n--- a/target/arm/cpu.h\n+++ b/target/arm/cpu.h\n@@ -1231,7 +1231,7 @@ extern const VMStateDescription vmstate_arm_cpu;\n void arm_cpu_do_interrupt(CPUState *cpu);\n void arm_v7m_cpu_do_interrupt(CPUState *cpu);\n \n-hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,\n+hwaddr arm_cpu_get_phys_addr_attrs_debug(CPUState *cpu, vaddr addr,\n MemTxAttrs *attrs);\n \n typedef struct ARMGranuleProtectionConfig {\ndiff --git a/target/arm/ptw.c b/target/arm/ptw.c\nindex 7b993bb5b3..f5f624c7c3 100644\n--- a/target/arm/ptw.c\n+++ b/target/arm/ptw.c\n@@ -3943,7 +3943,7 @@ static hwaddr arm_cpu_get_phys_page(CPUARMState *env, vaddr addr,\n return res.f.phys_addr;\n }\n \n-hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,\n+hwaddr arm_cpu_get_phys_addr_attrs_debug(CPUState *cs, vaddr addr,\n MemTxAttrs *attrs)\n {\n ARMCPU *cpu = ARM_CPU(cs);\ndiff --git a/target/avr/cpu.c b/target/avr/cpu.c\nindex 8579a7283b..3591219212 100644\n--- a/target/avr/cpu.c\n+++ b/target/avr/cpu.c\n@@ -233,7 +233,7 @@ static void avr_cpu_dump_state(CPUState *cs, FILE *f, int flags)\n \n static const struct SysemuCPUOps avr_sysemu_ops = {\n .has_work = avr_cpu_has_work,\n- .get_phys_page_debug = avr_cpu_get_phys_page_debug,\n+ .get_phys_addr_debug = avr_cpu_get_phys_addr_debug,\n };\n \n static const TCGCPUOps avr_tcg_ops = {\ndiff --git a/target/avr/cpu.h b/target/avr/cpu.h\nindex 518e243d81..7ebdc7b953 100644\n--- a/target/avr/cpu.h\n+++ b/target/avr/cpu.h\n@@ -178,7 +178,7 @@ extern const struct VMStateDescription vms_avr_cpu;\n \n void avr_cpu_do_interrupt(CPUState *cpu);\n bool avr_cpu_exec_interrupt(CPUState *cpu, int int_req);\n-hwaddr avr_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);\n+hwaddr avr_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr);\n int avr_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);\n int avr_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);\n int avr_print_insn(bfd_vma addr, disassemble_info *info);\ndiff --git a/target/avr/helper.c b/target/avr/helper.c\nindex 365c8c60e1..f3be8483b2 100644\n--- a/target/avr/helper.c\n+++ b/target/avr/helper.c\n@@ -107,7 +107,7 @@ void avr_cpu_do_interrupt(CPUState *cs)\n qemu_plugin_vcpu_interrupt_cb(cs, ret);\n }\n \n-hwaddr avr_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)\n+hwaddr avr_cpu_get_phys_addr_debug(CPUState *cs, vaddr addr)\n {\n return addr; /* I assume 1:1 address correspondence */\n }\ndiff --git a/target/hppa/cpu.c b/target/hppa/cpu.c\nindex 92027d129a..6443122cf1 100644\n--- a/target/hppa/cpu.c\n+++ b/target/hppa/cpu.c\n@@ -244,7 +244,7 @@ static ObjectClass *hppa_cpu_class_by_name(const char *cpu_model)\n \n static const struct SysemuCPUOps hppa_sysemu_ops = {\n .has_work = hppa_cpu_has_work,\n- .get_phys_page_debug = hppa_cpu_get_phys_page_debug,\n+ .get_phys_addr_debug = hppa_cpu_get_phys_addr_debug,\n };\n #endif\n \ndiff --git a/target/hppa/cpu.h b/target/hppa/cpu.h\nindex 7d47afe8ef..8a859d27b0 100644\n--- a/target/hppa/cpu.h\n+++ b/target/hppa/cpu.h\n@@ -389,7 +389,7 @@ int hppa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);\n void hppa_cpu_dump_state(CPUState *cs, FILE *f, int);\n #ifndef CONFIG_USER_ONLY\n void hppa_ptlbe(CPUHPPAState *env);\n-hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr);\n+hwaddr hppa_cpu_get_phys_addr_debug(CPUState *cs, vaddr addr);\n void hppa_set_ior_and_isr(CPUHPPAState *env, vaddr addr, bool mmu_disabled);\n bool hppa_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out, vaddr addr,\n MMUAccessType access_type, int mmu_idx,\ndiff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c\nindex ffbad8acfd..f507649226 100644\n--- a/target/hppa/mem_helper.c\n+++ b/target/hppa/mem_helper.c\n@@ -345,7 +345,7 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx,\n return ret;\n }\n \n-hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)\n+hwaddr hppa_cpu_get_phys_addr_debug(CPUState *cs, vaddr addr)\n {\n HPPACPU *cpu = HPPA_CPU(cs);\n hwaddr phys;\ndiff --git a/target/i386/cpu.c b/target/i386/cpu.c\nindex c6fd1dc00e..be331cab25 100644\n--- a/target/i386/cpu.c\n+++ b/target/i386/cpu.c\n@@ -10691,7 +10691,7 @@ static const struct SysemuCPUOps i386_sysemu_ops = {\n .has_work = x86_cpu_has_work,\n .get_memory_mapping = x86_cpu_get_memory_mapping,\n .get_paging_enabled = x86_cpu_get_paging_enabled,\n- .get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug,\n+ .get_phys_addr_attrs_debug = x86_cpu_get_phys_addr_attrs_debug,\n .asidx_from_attrs = x86_asidx_from_attrs,\n .get_crash_info = x86_cpu_get_crash_info,\n .write_elf32_note = x86_cpu_write_elf32_note,\ndiff --git a/target/i386/cpu.h b/target/i386/cpu.h\nindex 0b539155c4..8615361cc9 100644\n--- a/target/i386/cpu.h\n+++ b/target/i386/cpu.h\n@@ -2580,7 +2580,7 @@ int cpu_x86_support_mca_broadcast(CPUX86State *env);\n #ifndef CONFIG_USER_ONLY\n int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request);\n \n-hwaddr x86_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,\n+hwaddr x86_cpu_get_phys_addr_attrs_debug(CPUState *cpu, vaddr addr,\n MemTxAttrs *attrs);\n int cpu_get_pic_interrupt(CPUX86State *s);\n \ndiff --git a/target/i386/helper.c b/target/i386/helper.c\nindex 108b02396d..8cc73f619a 100644\n--- a/target/i386/helper.c\n+++ b/target/i386/helper.c\n@@ -252,7 +252,7 @@ void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4)\n }\n \n #if !defined(CONFIG_USER_ONLY)\n-hwaddr x86_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,\n+hwaddr x86_cpu_get_phys_addr_attrs_debug(CPUState *cs, vaddr addr,\n MemTxAttrs *attrs)\n {\n X86CPU *cpu = X86_CPU(cs);\ndiff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c\nindex e56ae2b343..406ca0355c 100644\n--- a/target/i386/whpx/whpx-all.c\n+++ b/target/i386/whpx/whpx-all.c\n@@ -238,7 +238,7 @@ struct whpx_register_set {\n * e. Let the affected CPU run in the exclusive mode.\n * f. Restore the original handler and the exception exit bitmap.\n * Note that handling all corner cases related to IDT/GDT is harder\n- * than it may seem. See x86_cpu_get_phys_page_attrs_debug() for a\n+ * than it may seem. See x86_cpu_get_phys_addr_attrs_debug() for a\n * rough idea.\n *\n * 3. In order to properly support guest-level debugging in parallel with\ndiff --git a/target/loongarch/cpu-mmu.h b/target/loongarch/cpu-mmu.h\nindex 3286accc14..2d7ebb2d72 100644\n--- a/target/loongarch/cpu-mmu.h\n+++ b/target/loongarch/cpu-mmu.h\n@@ -97,7 +97,7 @@ TLBRet loongarch_ptw(CPULoongArchState *env, MMUContext *context,\n int access_type, int mmu_idx, int debug);\n void get_dir_base_width(CPULoongArchState *env, uint64_t *dir_base,\n uint64_t *dir_width, unsigned int level);\n-hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);\n+hwaddr loongarch_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr);\n uint64_t loongarch_palen_mask(CPULoongArchState *env);\n \n #endif /* LOONGARCH_CPU_MMU_H */\ndiff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c\nindex e22568c84a..43ba414ac5 100644\n--- a/target/loongarch/cpu.c\n+++ b/target/loongarch/cpu.c\n@@ -832,7 +832,7 @@ static void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags)\n static const struct SysemuCPUOps loongarch_sysemu_ops = {\n .has_work = loongarch_cpu_has_work,\n .write_elf64_note = loongarch_cpu_write_elf64_note,\n- .get_phys_page_debug = loongarch_cpu_get_phys_page_debug,\n+ .get_phys_addr_debug = loongarch_cpu_get_phys_addr_debug,\n };\n \n static int64_t loongarch_cpu_get_arch_id(CPUState *cs)\ndiff --git a/target/loongarch/cpu_helper.c b/target/loongarch/cpu_helper.c\nindex 6044168766..181b931130 100644\n--- a/target/loongarch/cpu_helper.c\n+++ b/target/loongarch/cpu_helper.c\n@@ -354,7 +354,7 @@ TLBRet get_physical_address(CPULoongArchState *env, MMUContext *context,\n return loongarch_map_address(env, context, access_type, mmu_idx, is_debug);\n }\n \n-hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)\n+hwaddr loongarch_cpu_get_phys_addr_debug(CPUState *cs, vaddr addr)\n {\n CPULoongArchState *env = cpu_env(cs);\n MMUContext context;\ndiff --git a/target/m68k/cpu.c b/target/m68k/cpu.c\nindex d849a4a90f..425efdf7cc 100644\n--- a/target/m68k/cpu.c\n+++ b/target/m68k/cpu.c\n@@ -606,7 +606,7 @@ static const VMStateDescription vmstate_m68k_cpu = {\n \n static const struct SysemuCPUOps m68k_sysemu_ops = {\n .has_work = m68k_cpu_has_work,\n- .get_phys_page_debug = m68k_cpu_get_phys_page_debug,\n+ .get_phys_addr_debug = m68k_cpu_get_phys_addr_debug,\n };\n #endif /* !CONFIG_USER_ONLY */\n \ndiff --git a/target/m68k/cpu.h b/target/m68k/cpu.h\nindex 7911ab9de3..b181d5f981 100644\n--- a/target/m68k/cpu.h\n+++ b/target/m68k/cpu.h\n@@ -186,7 +186,7 @@ struct M68kCPUClass {\n #ifndef CONFIG_USER_ONLY\n void m68k_cpu_do_interrupt(CPUState *cpu);\n bool m68k_cpu_exec_interrupt(CPUState *cpu, int int_req);\n-hwaddr m68k_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);\n+hwaddr m68k_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr);\n #endif /* !CONFIG_USER_ONLY */\n void m68k_cpu_dump_state(CPUState *cpu, FILE *f, int flags);\n int m68k_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);\ndiff --git a/target/m68k/helper.c b/target/m68k/helper.c\nindex 9bab184389..2dd9ec1bdc 100644\n--- a/target/m68k/helper.c\n+++ b/target/m68k/helper.c\n@@ -907,7 +907,7 @@ txfail:\n return -1;\n }\n \n-hwaddr m68k_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)\n+hwaddr m68k_cpu_get_phys_addr_debug(CPUState *cs, vaddr addr)\n {\n CPUM68KState *env = cpu_env(cs);\n hwaddr phys_addr;\ndiff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c\nindex ec513ae82d..20fffccb60 100644\n--- a/target/microblaze/cpu.c\n+++ b/target/microblaze/cpu.c\n@@ -428,7 +428,7 @@ static ObjectClass *mb_cpu_class_by_name(const char *cpu_model)\n \n static const struct SysemuCPUOps mb_sysemu_ops = {\n .has_work = mb_cpu_has_work,\n- .get_phys_page_attrs_debug = mb_cpu_get_phys_page_attrs_debug,\n+ .get_phys_addr_attrs_debug = mb_cpu_get_phys_addr_attrs_debug,\n };\n #endif\n \ndiff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h\nindex d26b933b6d..d42565808f 100644\n--- a/target/microblaze/cpu.h\n+++ b/target/microblaze/cpu.h\n@@ -370,7 +370,7 @@ struct MicroBlazeCPUClass {\n #ifndef CONFIG_USER_ONLY\n void mb_cpu_do_interrupt(CPUState *cs);\n bool mb_cpu_exec_interrupt(CPUState *cs, int int_req);\n-hwaddr mb_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,\n+hwaddr mb_cpu_get_phys_addr_attrs_debug(CPUState *cpu, vaddr addr,\n MemTxAttrs *attrs);\n #endif /* !CONFIG_USER_ONLY */\n G_NORETURN void mb_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,\ndiff --git a/target/microblaze/helper.c b/target/microblaze/helper.c\nindex da8abe063e..f81c4f625b 100644\n--- a/target/microblaze/helper.c\n+++ b/target/microblaze/helper.c\n@@ -280,7 +280,7 @@ void mb_cpu_do_interrupt(CPUState *cs)\n }\n }\n \n-hwaddr mb_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,\n+hwaddr mb_cpu_get_phys_addr_attrs_debug(CPUState *cs, vaddr addr,\n MemTxAttrs *attrs)\n {\n MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);\ndiff --git a/target/mips/cpu.c b/target/mips/cpu.c\nindex 5f88c077db..6ef18105b9 100644\n--- a/target/mips/cpu.c\n+++ b/target/mips/cpu.c\n@@ -535,7 +535,7 @@ static ObjectClass *mips_cpu_class_by_name(const char *cpu_model)\n \n static const struct SysemuCPUOps mips_sysemu_ops = {\n .has_work = mips_cpu_has_work,\n- .get_phys_page_debug = mips_cpu_get_phys_page_debug,\n+ .get_phys_addr_debug = mips_cpu_get_phys_addr_debug,\n .legacy_vmsd = &vmstate_mips_cpu,\n };\n #endif\ndiff --git a/target/mips/internal.h b/target/mips/internal.h\nindex 28eb28936b..24bfa1903c 100644\n--- a/target/mips/internal.h\n+++ b/target/mips/internal.h\n@@ -115,7 +115,7 @@ enum {\n int get_physical_address(CPUMIPSState *env, hwaddr *physical,\n int *prot, target_ulong real_address,\n MMUAccessType access_type, int mmu_idx);\n-hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);\n+hwaddr mips_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr);\n \n typedef struct r4k_tlb_t r4k_tlb_t;\n struct r4k_tlb_t {\ndiff --git a/target/mips/system/physaddr.c b/target/mips/system/physaddr.c\nindex b8e1a5ac98..fbbbcf6e00 100644\n--- a/target/mips/system/physaddr.c\n+++ b/target/mips/system/physaddr.c\n@@ -228,7 +228,7 @@ int get_physical_address(CPUMIPSState *env, hwaddr *physical,\n return ret;\n }\n \n-hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)\n+hwaddr mips_cpu_get_phys_addr_debug(CPUState *cs, vaddr addr)\n {\n CPUMIPSState *env = cpu_env(cs);\n hwaddr phys_addr;\ndiff --git a/target/or1k/cpu.c b/target/or1k/cpu.c\nindex 3d1c22bf75..ea29b2e01f 100644\n--- a/target/or1k/cpu.c\n+++ b/target/or1k/cpu.c\n@@ -247,7 +247,7 @@ static void openrisc_any_initfn(Object *obj)\n \n static const struct SysemuCPUOps openrisc_sysemu_ops = {\n .has_work = openrisc_cpu_has_work,\n- .get_phys_page_debug = openrisc_cpu_get_phys_page_debug,\n+ .get_phys_addr_debug = openrisc_cpu_get_phys_addr_debug,\n };\n #endif\n \ndiff --git a/target/or1k/cpu.h b/target/or1k/cpu.h\nindex c8e2827930..8f20b9a122 100644\n--- a/target/or1k/cpu.h\n+++ b/target/or1k/cpu.h\n@@ -297,7 +297,7 @@ void openrisc_translate_code(CPUState *cs, TranslationBlock *tb,\n int print_insn_or1k(bfd_vma addr, disassemble_info *info);\n \n #ifndef CONFIG_USER_ONLY\n-hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);\n+hwaddr openrisc_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr);\n \n bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,\n MMUAccessType access_type, int mmu_idx,\ndiff --git a/target/or1k/mmu.c b/target/or1k/mmu.c\nindex 315debaf3e..3ff288a1f9 100644\n--- a/target/or1k/mmu.c\n+++ b/target/or1k/mmu.c\n@@ -138,7 +138,7 @@ bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr addr, int size,\n cpu_loop_exit_restore(cs, retaddr);\n }\n \n-hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)\n+hwaddr openrisc_cpu_get_phys_addr_debug(CPUState *cs, vaddr addr)\n {\n OpenRISCCPU *cpu = OPENRISC_CPU(cs);\n int prot, excp, sr = cpu->env.sr;\ndiff --git a/target/ppc/cpu.h b/target/ppc/cpu.h\nindex d637a50798..24a53ee2e1 100644\n--- a/target/ppc/cpu.h\n+++ b/target/ppc/cpu.h\n@@ -1639,7 +1639,7 @@ void ppc_cpu_dump_state(CPUState *cpu, FILE *f, int flags);\n int ppc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);\n int ppc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);\n #ifndef CONFIG_USER_ONLY\n-hwaddr ppc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);\n+hwaddr ppc_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr);\n #endif\n int ppc64_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,\n int cpuid, DumpState *s);\ndiff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c\nindex 191f5726f6..d25f69f13b 100644\n--- a/target/ppc/cpu_init.c\n+++ b/target/ppc/cpu_init.c\n@@ -7477,7 +7477,7 @@ static void ppc_disas_set_info(const CPUState *cs, disassemble_info *info)\n \n static const struct SysemuCPUOps ppc_sysemu_ops = {\n .has_work = ppc_cpu_has_work,\n- .get_phys_page_debug = ppc_cpu_get_phys_page_debug,\n+ .get_phys_addr_debug = ppc_cpu_get_phys_addr_debug,\n .write_elf32_note = ppc32_cpu_write_elf32_note,\n .write_elf64_note = ppc64_cpu_write_elf64_note,\n .internal_is_big_endian = ppc_cpu_is_big_endian,\ndiff --git a/target/ppc/mmu-hash32.c b/target/ppc/mmu-hash32.c\nindex 8b980a5aa9..43d581cadf 100644\n--- a/target/ppc/mmu-hash32.c\n+++ b/target/ppc/mmu-hash32.c\n@@ -131,7 +131,7 @@ static bool ppc_hash32_direct_store(PowerPCCPU *cpu, target_ulong sr,\n }\n \n /*\n- * From ppc_cpu_get_phys_page_debug, env->access_type is not set.\n+ * From ppc_cpu_get_phys_addr_debug, env->access_type is not set.\n * Assume ACCESS_INT for that case.\n */\n switch (guest_visible ? env->access_type : ACCESS_INT) {\ndiff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c\nindex a1345df716..2499e619f8 100644\n--- a/target/ppc/mmu_common.c\n+++ b/target/ppc/mmu_common.c\n@@ -848,7 +848,7 @@ bool ppc_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type,\n }\n }\n \n-hwaddr ppc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)\n+hwaddr ppc_cpu_get_phys_addr_debug(CPUState *cs, vaddr addr)\n {\n PowerPCCPU *cpu = POWERPC_CPU(cs);\n hwaddr raddr;\ndiff --git a/target/riscv/cpu.c b/target/riscv/cpu.c\nindex 8ac935ac06..e5d8592ef2 100644\n--- a/target/riscv/cpu.c\n+++ b/target/riscv/cpu.c\n@@ -2717,7 +2717,7 @@ static int64_t riscv_get_arch_id(CPUState *cs)\n \n static const struct SysemuCPUOps riscv_sysemu_ops = {\n .has_work = riscv_cpu_has_work,\n- .get_phys_page_debug = riscv_cpu_get_phys_page_debug,\n+ .get_phys_addr_debug = riscv_cpu_get_phys_addr_debug,\n .write_elf64_note = riscv_cpu_write_elf64_note,\n .write_elf32_note = riscv_cpu_write_elf32_note,\n .legacy_vmsd = &vmstate_riscv_cpu,\ndiff --git a/target/riscv/cpu.h b/target/riscv/cpu.h\nindex 35d1f6362c..111afe19d1 100644\n--- a/target/riscv/cpu.h\n+++ b/target/riscv/cpu.h\n@@ -629,7 +629,7 @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,\n MMUAccessType access_type,\n int mmu_idx, MemTxAttrs attrs,\n MemTxResult response, uintptr_t retaddr);\n-hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);\n+hwaddr riscv_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr);\n bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);\n void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env);\n int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts);\ndiff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c\nindex 475e9cfd57..584a3928a4 100644\n--- a/target/riscv/cpu_helper.c\n+++ b/target/riscv/cpu_helper.c\n@@ -1657,7 +1657,7 @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,\n env->two_stage_indirect_lookup = two_stage_indirect;\n }\n \n-hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)\n+hwaddr riscv_cpu_get_phys_addr_debug(CPUState *cs, vaddr addr)\n {\n RISCVCPU *cpu = RISCV_CPU(cs);\n CPURISCVState *env = &cpu->env;\ndiff --git a/target/rx/cpu.c b/target/rx/cpu.c\nindex b5284199e6..20b188c24c 100644\n--- a/target/rx/cpu.c\n+++ b/target/rx/cpu.c\n@@ -209,7 +209,7 @@ static void rx_cpu_init(Object *obj)\n \n static const struct SysemuCPUOps rx_sysemu_ops = {\n .has_work = rx_cpu_has_work,\n- .get_phys_page_debug = rx_cpu_get_phys_page_debug,\n+ .get_phys_addr_debug = rx_cpu_get_phys_addr_debug,\n };\n \n static const TCGCPUOps rx_tcg_ops = {\ndiff --git a/target/rx/cpu.h b/target/rx/cpu.h\nindex b3b1ecff5a..328521791b 100644\n--- a/target/rx/cpu.h\n+++ b/target/rx/cpu.h\n@@ -137,7 +137,7 @@ struct RXCPUClass {\n const char *rx_crname(uint8_t cr);\n void rx_cpu_do_interrupt(CPUState *cpu);\n bool rx_cpu_exec_interrupt(CPUState *cpu, int int_req);\n-hwaddr rx_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);\n+hwaddr rx_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr);\n void rx_cpu_dump_state(CPUState *cpu, FILE *f, int flags);\n int rx_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);\n int rx_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);\ndiff --git a/target/rx/helper.c b/target/rx/helper.c\nindex daaeeec1b5..0f99279bba 100644\n--- a/target/rx/helper.c\n+++ b/target/rx/helper.c\n@@ -147,7 +147,7 @@ bool rx_cpu_exec_interrupt(CPUState *cs, int interrupt_request)\n return false;\n }\n \n-hwaddr rx_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)\n+hwaddr rx_cpu_get_phys_addr_debug(CPUState *cs, vaddr addr)\n {\n return addr;\n }\ndiff --git a/target/s390x/cpu-system.c b/target/s390x/cpu-system.c\nindex c133b0c262..1bd3721d10 100644\n--- a/target/s390x/cpu-system.c\n+++ b/target/s390x/cpu-system.c\n@@ -176,7 +176,7 @@ void s390_cpu_finalize(Object *obj)\n \n static const struct SysemuCPUOps s390_sysemu_ops = {\n .has_work = s390_cpu_has_work,\n- .get_phys_page_debug = s390_cpu_get_phys_addr_debug,\n+ .get_phys_addr_debug = s390_cpu_get_phys_addr_debug,\n .get_crash_info = s390_cpu_get_crash_info,\n .write_elf64_note = s390_cpu_write_elf64_note,\n .legacy_vmsd = &vmstate_s390_cpu,\ndiff --git a/target/sh4/cpu.c b/target/sh4/cpu.c\nindex e2bde45761..40d5fde76d 100644\n--- a/target/sh4/cpu.c\n+++ b/target/sh4/cpu.c\n@@ -278,7 +278,7 @@ static const VMStateDescription vmstate_sh_cpu = {\n \n static const struct SysemuCPUOps sh4_sysemu_ops = {\n .has_work = superh_cpu_has_work,\n- .get_phys_page_debug = superh_cpu_get_phys_page_debug,\n+ .get_phys_addr_debug = superh_cpu_get_phys_addr_debug,\n };\n #endif\n \ndiff --git a/target/sh4/cpu.h b/target/sh4/cpu.h\nindex b0759010c4..3743452190 100644\n--- a/target/sh4/cpu.h\n+++ b/target/sh4/cpu.h\n@@ -252,7 +252,7 @@ void sh4_translate_code(CPUState *cs, TranslationBlock *tb,\n int *max_insns, vaddr pc, void *host_pc);\n \n #if !defined(CONFIG_USER_ONLY)\n-hwaddr superh_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);\n+hwaddr superh_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr);\n bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size,\n MMUAccessType access_type, int mmu_idx,\n bool probe, uintptr_t retaddr);\ndiff --git a/target/sh4/helper.c b/target/sh4/helper.c\nindex 5d6295618f..b3ec7ce64d 100644\n--- a/target/sh4/helper.c\n+++ b/target/sh4/helper.c\n@@ -435,7 +435,7 @@ static int get_physical_address(CPUSH4State *env, hwaddr* physical,\n return get_mmu_address(env, physical, prot, address, access_type);\n }\n \n-hwaddr superh_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)\n+hwaddr superh_cpu_get_phys_addr_debug(CPUState *cs, vaddr addr)\n {\n hwaddr physical;\n int prot;\ndiff --git a/target/sparc/cpu.c b/target/sparc/cpu.c\nindex 1493336e7a..d5a08928e5 100644\n--- a/target/sparc/cpu.c\n+++ b/target/sparc/cpu.c\n@@ -997,7 +997,7 @@ static const Property sparc_cpu_properties[] = {\n \n static const struct SysemuCPUOps sparc_sysemu_ops = {\n .has_work = sparc_cpu_has_work,\n- .get_phys_page_debug = sparc_cpu_get_phys_page_debug,\n+ .get_phys_addr_debug = sparc_cpu_get_phys_addr_debug,\n .legacy_vmsd = &vmstate_sparc_cpu,\n };\n #endif\ndiff --git a/target/sparc/cpu.h b/target/sparc/cpu.h\nindex 0139732e4c..307b98b76c 100644\n--- a/target/sparc/cpu.h\n+++ b/target/sparc/cpu.h\n@@ -580,7 +580,7 @@ struct SPARCCPUClass {\n #ifndef CONFIG_USER_ONLY\n extern const VMStateDescription vmstate_sparc_cpu;\n \n-hwaddr sparc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);\n+hwaddr sparc_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr);\n #endif\n \n void sparc_cpu_do_interrupt(CPUState *cpu);\ndiff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c\nindex 25f8a85fae..34b212a7aa 100644\n--- a/target/sparc/mmu_helper.c\n+++ b/target/sparc/mmu_helper.c\n@@ -902,7 +902,7 @@ hwaddr cpu_get_phys_page_nofault(CPUSPARCState *env, target_ulong addr,\n }\n #endif\n \n-hwaddr sparc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)\n+hwaddr sparc_cpu_get_phys_addr_debug(CPUState *cs, vaddr addr)\n {\n CPUSPARCState *env = cpu_env(cs);\n hwaddr phys_addr;\ndiff --git a/target/tricore/cpu.c b/target/tricore/cpu.c\nindex 04319e107b..472c24ae32 100644\n--- a/target/tricore/cpu.c\n+++ b/target/tricore/cpu.c\n@@ -176,7 +176,7 @@ static bool tricore_cpu_exec_interrupt(CPUState *cs, int interrupt_request)\n \n static const struct SysemuCPUOps tricore_sysemu_ops = {\n .has_work = tricore_cpu_has_work,\n- .get_phys_page_debug = tricore_cpu_get_phys_page_debug,\n+ .get_phys_addr_debug = tricore_cpu_get_phys_addr_debug,\n };\n \n static const TCGCPUOps tricore_tcg_ops = {\ndiff --git a/target/tricore/cpu.h b/target/tricore/cpu.h\nindex ab46192e26..56241b491f 100644\n--- a/target/tricore/cpu.h\n+++ b/target/tricore/cpu.h\n@@ -80,7 +80,7 @@ struct TriCoreCPUClass {\n ResettablePhases parent_phases;\n };\n \n-hwaddr tricore_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);\n+hwaddr tricore_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr);\n void tricore_cpu_dump_state(CPUState *cpu, FILE *f, int flags);\n \n FIELD(PCXI, PCPN_13, 24, 8)\ndiff --git a/target/tricore/helper.c b/target/tricore/helper.c\nindex 7ee8c7fd69..ce1693622b 100644\n--- a/target/tricore/helper.c\n+++ b/target/tricore/helper.c\n@@ -46,7 +46,7 @@ static int get_physical_address(CPUTriCoreState *env, hwaddr *physical,\n return ret;\n }\n \n-hwaddr tricore_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)\n+hwaddr tricore_cpu_get_phys_addr_debug(CPUState *cs, vaddr addr)\n {\n TriCoreCPU *cpu = TRICORE_CPU(cs);\n hwaddr phys_addr;\ndiff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c\nindex eebf40559b..8a22f1a08e 100644\n--- a/target/xtensa/cpu.c\n+++ b/target/xtensa/cpu.c\n@@ -303,7 +303,7 @@ static const VMStateDescription vmstate_xtensa_cpu = {\n \n static const struct SysemuCPUOps xtensa_sysemu_ops = {\n .has_work = xtensa_cpu_has_work,\n- .get_phys_page_debug = xtensa_cpu_get_phys_page_debug,\n+ .get_phys_addr_debug = xtensa_cpu_get_phys_addr_debug,\n };\n #endif\n \ndiff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h\nindex 2219292484..546a5e76a6 100644\n--- a/target/xtensa/cpu.h\n+++ b/target/xtensa/cpu.h\n@@ -591,7 +591,7 @@ void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,\n unsigned size, MMUAccessType access_type,\n int mmu_idx, MemTxAttrs attrs,\n MemTxResult response, uintptr_t retaddr);\n-hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);\n+hwaddr xtensa_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr);\n bool xtensa_debug_check_breakpoint(CPUState *cs);\n #endif\n void xtensa_cpu_dump_state(CPUState *cpu, FILE *f, int flags);\ndiff --git a/target/xtensa/mmu_helper.c b/target/xtensa/mmu_helper.c\nindex 71330fc84b..a126f6b671 100644\n--- a/target/xtensa/mmu_helper.c\n+++ b/target/xtensa/mmu_helper.c\n@@ -316,7 +316,7 @@ static void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb,\n }\n }\n \n-hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)\n+hwaddr xtensa_cpu_get_phys_addr_debug(CPUState *cs, vaddr addr)\n {\n XtensaCPU *cpu = XTENSA_CPU(cs);\n uint32_t paddr;\n","prefixes":["08/17"]}