{"id":2224620,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2224620/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417173105.1648172-4-peter.maydell@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260417173105.1648172-4-peter.maydell@linaro.org>","list_archive_url":null,"date":"2026-04-17T17:30:51","name":"[03/17] target/microblaze: Make get_phys_page_attrs_debug handle non-page-aligned addrs","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"6b5f8d77fc781385055b14e4385d7e48f8decbfc","submitter":{"id":5111,"url":"http://patchwork.ozlabs.org/api/1.2/people/5111/?format=json","name":"Peter Maydell","email":"peter.maydell@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417173105.1648172-4-peter.maydell@linaro.org/mbox/","series":[{"id":500380,"url":"http://patchwork.ozlabs.org/api/1.2/series/500380/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500380","date":"2026-04-17T17:30:51","name":"Handle sub-page granularity in cpu_memory_rw_debug()","version":1,"mbox":"http://patchwork.ozlabs.org/series/500380/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2224620/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2224620/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=byzywD4K;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fy25M05N7z1yDF\n\tfor ; Sat, 18 Apr 2026 03:32:39 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wDn2s-0006z2-EH; Fri, 17 Apr 2026 13:31:58 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wDn2G-0006jR-AM\n for qemu-devel@nongnu.org; Fri, 17 Apr 2026 13:31:30 -0400","from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wDn2B-00021a-AQ\n for qemu-devel@nongnu.org; Fri, 17 Apr 2026 13:31:17 -0400","by mail-wr1-x42c.google.com with SMTP id\n ffacd0b85a97d-43d73422431so706773f8f.2\n for ; Fri, 17 Apr 2026 10:31:13 -0700 (PDT)","from lanath.. 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Iglesias\" ,\n Jiaxun Yang , Nicholas Piggin ,\n Chinmay Rath , Glenn Miles ,\n Palmer Dabbelt ,\n Alistair Francis , Weiwei Li ,\n Daniel Henrique Barboza ,\n Liu Zhiwei ,\n Chao Liu , Ilya Leoshkevich ,\n David Hildenbrand ,\n Mark Cave-Ayland ,\n Artyom Tarasenko ","Subject":"[PATCH 03/17] target/microblaze: Make get_phys_page_attrs_debug\n handle non-page-aligned addrs","Date":"Fri, 17 Apr 2026 18:30:51 +0100","Message-ID":"<20260417173105.1648172-4-peter.maydell@linaro.org>","X-Mailer":"git-send-email 2.43.0","In-Reply-To":"<20260417173105.1648172-1-peter.maydell@linaro.org>","References":"<20260417173105.1648172-1-peter.maydell@linaro.org>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2a00:1450:4864:20::42c;\n envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Currently our implementations of SysemuCPUOps::get_phys_page_debug\nand SysemuCPUOps::get_phys_page_attrs_debug are a mix of \"accepts a\nnon-page-aligned virtual address and returns the corresponding\nnon-page-aligned physical address\" and \"only returns a page-aligned\nphysical address\". This is awkward for callsites, which in practice\nall want the physical address for an arbitrary virtual address and\nhave to work around the possibility of getting a page-aligned\naddress, and it doesn't account for protection being possibly on a\nsub-page-sized granularity. We want to standardize on the\nimplementation having to handle non-page-aligned addresses.\n\nFor microblaze, we just need to remove the explicit rounding down to\nthe page boundary that we were doing in\nmb_cpu_get_phys_page_attrs_debug() when calculating the output\nphysaddr from the results of the MMU lookup.\n\nSigned-off-by: Peter Maydell \n---\n target/microblaze/helper.c | 9 ++++-----\n 1 file changed, 4 insertions(+), 5 deletions(-)","diff":"diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c\nindex a1857b7217..da8abe063e 100644\n--- a/target/microblaze/helper.c\n+++ b/target/microblaze/helper.c\n@@ -284,7 +284,6 @@ hwaddr mb_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,\n MemTxAttrs *attrs)\n {\n MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);\n- vaddr vaddr;\n hwaddr paddr = 0;\n MicroBlazeMMULookup lu;\n int mmu_idx = cpu_mmu_index(cs, false);\n@@ -297,12 +296,12 @@ hwaddr mb_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,\n if (mmu_idx != MMU_NOMMU_IDX) {\n hit = mmu_translate(cpu, &lu, addr, 0, 0);\n if (hit) {\n- vaddr = addr & TARGET_PAGE_MASK;\n- paddr = lu.paddr + vaddr - lu.vaddr;\n+ paddr = lu.paddr + addr - lu.vaddr;\n } else\n paddr = 0; /* ???. */\n- } else\n- paddr = addr & TARGET_PAGE_MASK;\n+ } else {\n+ paddr = addr;\n+ }\n \n return paddr;\n }\n","prefixes":["03/17"]}