{"id":2224597,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2224597/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417164328.1009132-7-alex.bennee@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260417164328.1009132-7-alex.bennee@linaro.org>","list_archive_url":null,"date":"2026-04-17T16:43:26","name":"[6/7] tests/tcg: create a mini-gic3 library","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"3ce35b8ebb62ea380068e47cd8c4e0edf110449e","submitter":{"id":39532,"url":"http://patchwork.ozlabs.org/api/1.2/people/39532/?format=json","name":"Alex Bennée","email":"alex.bennee@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417164328.1009132-7-alex.bennee@linaro.org/mbox/","series":[{"id":500373,"url":"http://patchwork.ozlabs.org/api/1.2/series/500373/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500373","date":"2026-04-17T16:43:20","name":"tests/tcg: more capabilities for aarch64-softmmu tests","version":1,"mbox":"http://patchwork.ozlabs.org/series/500373/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2224597/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2224597/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=YnTkU+yw;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2a00:1450:4864:20::42d;\n envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x42d.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Just enough GIC to trigger timer interrupts.\n\nSigned-off-by: Alex Bennée \n---\n tests/tcg/aarch64/system/lib/gicv3.h | 60 +++++++++++++++++++\n tests/tcg/aarch64/system/lib/gicv3.c | 70 +++++++++++++++++++++++\n tests/tcg/aarch64/Makefile.softmmu-target | 2 +\n 3 files changed, 132 insertions(+)\n create mode 100644 tests/tcg/aarch64/system/lib/gicv3.h\n create mode 100644 tests/tcg/aarch64/system/lib/gicv3.c","diff":"diff --git a/tests/tcg/aarch64/system/lib/gicv3.h b/tests/tcg/aarch64/system/lib/gicv3.h\nnew file mode 100644\nindex 00000000000..05c4c2f538b\n--- /dev/null\n+++ b/tests/tcg/aarch64/system/lib/gicv3.h\n@@ -0,0 +1,60 @@\n+/*\n+ * GICv3 Helper Library\n+ *\n+ * Copyright (c) 2026 Linaro Ltd\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+#ifndef GICV3_H\n+#define GICV3_H\n+\n+/*\n+ * This duplicates just the bits of hw/intc/gicv3_internal.h we\n+ * need for basic functionality.\n+ */\n+\n+/* Virt machine GICv3 base addresses */\n+#define GICD_BASE 0x08000000 /* c.f. VIRT_GIC_DIST */\n+#define GICR_BASE 0x080a0000 /* c.f. VIRT_GIC_REDIST */\n+\n+/* Distributor registers */\n+#define GICD_CTLR (GICD_BASE + 0x0000)\n+#define GICD_TYPER (GICD_BASE + 0x0004)\n+#define GICD_IIDR (GICD_BASE + 0x0008)\n+\n+/* Redistributor registers (per-CPU) */\n+#define GICR_SGI_OFFSET 0x00010000\n+\n+#define GICR_CTLR 0x0000\n+#define GICR_WAKER 0x0014\n+\n+#define GICR_IGROUPR0 (GICR_SGI_OFFSET + 0x0080)\n+#define GICR_ISENABLER0 (GICR_SGI_OFFSET + 0x0100)\n+#define GICR_IPRIORITYR (GICR_SGI_OFFSET + 0x0400)\n+\n+/* GICD_CTLR fields */\n+#define GICD_CTLR_ENA_GRP0 (1U << 0)\n+#define GICD_CTLR_ENA_GRP1NS (1U << 1)\n+#define GICD_CTLR_ARE_NS (1U << 5)\n+\n+/* GICR_WAKER bits */\n+#define GICR_WAKER_ProcessorSleep (1U << 1)\n+#define GICR_WAKER_ChildrenAsleep (1U << 2)\n+\n+/**\n+ * gicv3_init:\n+ *\n+ * Initialize GICv3 distributor and the redistributor for the current CPU.\n+ */\n+void gicv3_init(void);\n+\n+/**\n+ * gicv3_enable_irq:\n+ * @irq: The IRQ number to enable\n+ *\n+ * Enable the specified IRQ (SPI or PPI).\n+ */\n+void gicv3_enable_irq(unsigned int irq);\n+\n+#endif /* GICV3_H */\ndiff --git a/tests/tcg/aarch64/system/lib/gicv3.c b/tests/tcg/aarch64/system/lib/gicv3.c\nnew file mode 100644\nindex 00000000000..9cfd033a8ec\n--- /dev/null\n+++ b/tests/tcg/aarch64/system/lib/gicv3.c\n@@ -0,0 +1,70 @@\n+/*\n+ * GICv3 Helper Library Implementation\n+ *\n+ * Copyright (c) 2026 Linaro Ltd\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+#include \n+#include \"sysregs.h\"\n+#include \"gicv3.h\"\n+\n+static inline void write_reg(uintptr_t addr, uint32_t val)\n+{\n+ *(volatile uint32_t *) addr = val;\n+}\n+\n+static inline uint32_t read_reg(uintptr_t addr)\n+{\n+ return *(volatile uint32_t *) addr;\n+}\n+\n+void gicv3_init(void)\n+{\n+ uint32_t val;\n+\n+ /* 1. Enable Distributor ARE and Group 1 NS */\n+ val = read_reg(GICD_CTLR);\n+ val |= GICD_CTLR_ARE_NS | GICD_CTLR_ENA_GRP1NS;\n+ write_reg(GICD_CTLR, val);\n+\n+ /* 2. Wake up Redistributor 0 and clear ProcessorSleep */\n+ val = read_reg(GICR_BASE + GICR_WAKER);\n+ val &= ~GICR_WAKER_ProcessorSleep;\n+ write_reg(GICR_BASE + GICR_WAKER, val);\n+\n+ /* Wait for ChildrenAsleep to be cleared */\n+ while (read_reg(GICR_BASE + GICR_WAKER) & GICR_WAKER_ChildrenAsleep) {\n+ /* spin */\n+ }\n+\n+ /* 3. Enable CPU interface */\n+ /* Set Priority Mask to allow all interrupts */\n+ write_sysreg(0xff, ICC_PMR_EL1);\n+ /* Enable Group 1 Non-Secure interrupts */\n+ write_sysreg(1, ICC_IGRPEN1_EL1);\n+ isb();\n+}\n+\n+void gicv3_enable_irq(unsigned int irq)\n+{\n+ if (irq < 32) {\n+ /* PPI: use GICR_ISENABLER0 */\n+ uintptr_t addr;\n+\n+ /* Set Group 1 */\n+ addr = GICR_BASE + GICR_IGROUPR0;\n+ write_reg(addr, read_reg(addr) | (1U << irq));\n+\n+ /* Set priority (0xa0) */\n+ addr = GICR_BASE + GICR_IPRIORITYR + irq;\n+ *(volatile uint8_t *)addr = 0xa0;\n+\n+ /* Enable it */\n+ addr = GICR_BASE + GICR_ISENABLER0;\n+ write_reg(addr, 1U << irq);\n+ } else {\n+ /* SPI: not implemented yet */\n+ }\n+}\ndiff --git a/tests/tcg/aarch64/Makefile.softmmu-target b/tests/tcg/aarch64/Makefile.softmmu-target\nindex 5770ae1fb0c..543d638e819 100644\n--- a/tests/tcg/aarch64/Makefile.softmmu-target\n+++ b/tests/tcg/aarch64/Makefile.softmmu-target\n@@ -106,6 +106,8 @@ run-pauth-3:\n \t$(call skip-test, \"RUN of pauth-3\", \"not built\")\n endif\n \n+gicv3.o: gicv3.c gicv3.h\n+\t$(CC) $(CFLAGS) $(EXTRA_CFLAGS) -c $< -o $@\n ifneq ($(CROSS_CC_HAS_ARMV8_MTE),)\n QEMU_MTE_ENABLED_MACHINE=-M virt,mte=on -cpu max -display none\n QEMU_OPTS_WITH_MTE_ON = $(QEMU_MTE_ENABLED_MACHINE) $(QEMU_BASE_ARGS) -kernel\n","prefixes":["6/7"]}