{"id":2224584,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2224584/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417164328.1009132-5-alex.bennee@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260417164328.1009132-5-alex.bennee@linaro.org>","list_archive_url":null,"date":"2026-04-17T16:43:24","name":"[4/7] tests/tcg: move aarch64 page table setup to c code","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"edb0a5b03a2fd4876ddb424674b3751524559ad0","submitter":{"id":39532,"url":"http://patchwork.ozlabs.org/api/1.2/people/39532/?format=json","name":"Alex Bennée","email":"alex.bennee@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417164328.1009132-5-alex.bennee@linaro.org/mbox/","series":[{"id":500373,"url":"http://patchwork.ozlabs.org/api/1.2/series/500373/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500373","date":"2026-04-17T16:43:20","name":"tests/tcg: more capabilities for aarch64-softmmu tests","version":1,"mbox":"http://patchwork.ozlabs.org/series/500373/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2224584/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2224584/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=rzR5YZT2;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2a00:1450:4864:20::32e;\n envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32e.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"If we want more flexibility messing around with page tables lets do it\nwithout having to rely on assembly for it.\n\nSigned-off-by: Alex Bennée \n\n---\nAJB\n - a result of -O0 does mean each helper ends up with a stack frame\n being needed to do the relatively simple mask and shift. I've\n experimented with -O1 and trying to manually enable inlining but\n couldn't get anything to work.\n---\n tests/tcg/aarch64/system/lib/pgtable.h | 80 ++++++++++++++++\n tests/tcg/aarch64/system/lib/sysregs.h | 20 ++++\n tests/tcg/aarch64/system/lib/pgtable.c | 60 ++++++++++++\n tests/tcg/aarch64/Makefile.softmmu-target | 9 +-\n tests/tcg/aarch64/system/boot.S | 109 +---------------------\n tests/tcg/aarch64/system/kernel.ld | 3 +\n 6 files changed, 170 insertions(+), 111 deletions(-)\n create mode 100644 tests/tcg/aarch64/system/lib/pgtable.h\n create mode 100644 tests/tcg/aarch64/system/lib/pgtable.c","diff":"diff --git a/tests/tcg/aarch64/system/lib/pgtable.h b/tests/tcg/aarch64/system/lib/pgtable.h\nnew file mode 100644\nindex 00000000000..c5048c3eea1\n--- /dev/null\n+++ b/tests/tcg/aarch64/system/lib/pgtable.h\n@@ -0,0 +1,80 @@\n+/*\n+ * AArch64 page table helpers\n+ *\n+ * Some simple helper functions for setting the page table entries.\n+ *\n+ * Copyright (C) 2026 Linaro Ltd.\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+/*\n+ * Page Table Descriptors\n+ */\n+#define DESC_VALID (1ULL << 0)\n+#define DESC_TYPE_TABLE (1ULL << 1)\n+#define DESC_TYPE_BLOCK (0ULL << 1)\n+#define DESC_TYPE_PAGE (1ULL << 1)\n+\n+#define DESC_AF (1ULL << 10)\n+#define DESC_ATTRINDX(i) ((uint64_t)(i) << 2)\n+#define DESC_NS (1ULL << 5)\n+#define DESC_UXN (1ULL << 53)\n+#define DESC_PXN (1ULL << 54)\n+\n+#define DESC_ADDR_MASK 0x0000FFFFFFFFF000ULL\n+#define DESC_ADDR_BLOCK_L1 0x0000FFFFC0000000ULL\n+#define DESC_ADDR_BLOCK_L2 0x0000FFFFFFE00000ULL\n+\n+/* Stage 2 specific */\n+#define DESC_S2_AP_RW (3ULL << 6)\n+#define DESC_S2_MEMATTR_NORMAL (0xfULL << 2)\n+\n+/**\n+ * pgt_map_l1_table - Setup a Level 1 table pointing to a Level 2 table\n+ * @table: the level 1 table\n+ * @va: the virtual address to map\n+ * @next_table: the level 2 table to point to\n+ */\n+static inline void pgt_map_l1_table(uint64_t *table, uintptr_t va, uint64_t *next_table)\n+{\n+ int index = (va >> 30) & 0x1ff;\n+ table[index] = ((uintptr_t)next_table & DESC_ADDR_MASK) | DESC_TYPE_TABLE | DESC_VALID;\n+}\n+\n+/**\n+ * pgt_map_l1_block - Setup a Level 1 block mapping (1GB)\n+ * @table: the level 1 table\n+ * @va: the virtual address to map\n+ * @pa: the physical address to map to\n+ * @flags: the descriptor flags (e.g. DESC_AF | ...)\n+ */\n+static inline void pgt_map_l1_block(uint64_t *table, uintptr_t va, uintptr_t pa, uint64_t flags)\n+{\n+ int index = (va >> 30) & 0x1ff;\n+ table[index] = (pa & DESC_ADDR_BLOCK_L1) | flags | DESC_TYPE_BLOCK | DESC_VALID;\n+}\n+\n+/**\n+ * pgt_map_l2_block - Setup a Level 2 block mapping (2MB)\n+ * @table: the level 2 table\n+ * @va: the virtual address to map\n+ * @pa: the physical address to map to\n+ * @flags: the descriptor flags (e.g. DESC_AF | ...)\n+ */\n+static inline void pgt_map_l2_block(uint64_t *table, uintptr_t va, uintptr_t pa, uint64_t flags)\n+{\n+ int index = (va >> 21) & 0x1ff;\n+ table[index] = (pa & DESC_ADDR_BLOCK_L2) | flags | DESC_TYPE_BLOCK | DESC_VALID;\n+}\n+\n+/**\n+ * flat_map_stage2 - Setup a flat (VA==PA) stage 2 mapping\n+ * @table: the level 2 table\n+ * @addr: the VA/PA to map\n+ * @flags: the descriptor flags (e.g. DESC_AF | ...)\n+ */\n+static inline void flat_map_stage2(uint64_t *table, uintptr_t addr, uint64_t flags)\n+{\n+ pgt_map_l2_block(table, addr, addr, flags);\n+}\ndiff --git a/tests/tcg/aarch64/system/lib/sysregs.h b/tests/tcg/aarch64/system/lib/sysregs.h\nindex b1c465e0746..6e714f46842 100644\n--- a/tests/tcg/aarch64/system/lib/sysregs.h\n+++ b/tests/tcg/aarch64/system/lib/sysregs.h\n@@ -20,3 +20,23 @@\n asm volatile(\"msr \" __stringify(r) \", %x0\" \\\n : : \"rZ\" (__val)); \\\n } while (0)\n+\n+#define isb() asm volatile(\"isb\" : : : \"memory\")\n+#define dsb(opt) asm volatile(\"dsb \" #opt : : : \"memory\")\n+\n+/*\n+ * SCTLR_EL1 Bits\n+ */\n+#define SCTLR_EL1_M (1ULL << 0) /* enable MMU for EL0/1 */\n+#define SCTLR_EL1_C (1ULL << 2) /* Data cachability control */\n+#define SCTLR_EL1_SA (1ULL << 3) /* SP alignment check */\n+#define SCTLR_EL1_I (1ULL << 12) /* Instruction cachability control */\n+\n+/*\n+ * TCR_EL1 Bits\n+ */\n+#define TCR_EL1_T0SZ(s) ((s) & 0x3fULL)\n+#define TCR_EL1_IRGN0_WBWA (3ULL << 8)\n+#define TCR_EL1_ORGN0_WBWA (3ULL << 10)\n+#define TCR_EL1_IPS_40BIT (2ULL << 32)\n+#define TCR_EL1_TG0_4KB (0ULL << 14)\ndiff --git a/tests/tcg/aarch64/system/lib/pgtable.c b/tests/tcg/aarch64/system/lib/pgtable.c\nnew file mode 100644\nindex 00000000000..a558f5f0dd5\n--- /dev/null\n+++ b/tests/tcg/aarch64/system/lib/pgtable.c\n@@ -0,0 +1,60 @@\n+#include \n+#include \"sysregs.h\"\n+#include \"pgtable.h\"\n+\n+/*\n+ * Page table setup for AArch64 system tests.\n+ * We use a flat identity mapping.\n+ */\n+\n+/* Symbols defined in kernel.ld */\n+extern char _text_start[];\n+extern char _data_start[];\n+extern char _tag_start[];\n+\n+/* Assume these start zeroed */\n+uint64_t ttb_l1[512] __attribute__((aligned(4096)));\n+uint64_t ttb_l2[512] __attribute__((aligned(4096)));\n+\n+/*\n+ * Setup a flat address mapping page-tables. Stage one simply\n+ * maps RAM to the first Gb. The stage2 tables have two 2mb\n+ * translation block entries covering a series of adjacent\n+ * 4k pages.\n+ */\n+void setup_pgtables(void)\n+{\n+ /* L1 entry points to L2 table */\n+ pgt_map_l1_table(ttb_l1, (uintptr_t)_text_start, ttb_l2);\n+\n+ /* L2 entries: 2MB blocks */\n+ /* .text & .rodata (Read-only, executable) */\n+ flat_map_stage2(ttb_l2, (uintptr_t)_text_start, DESC_AF);\n+\n+ /* .data & .bss (Read-write, no-execute) */\n+ flat_map_stage2(ttb_l2, (uintptr_t)_data_start, DESC_AF | DESC_PXN | DESC_UXN);\n+\n+ /* mte_page (Read-write, no-execute, AttrIndx=1) */\n+ flat_map_stage2(ttb_l2, (uintptr_t)_tag_start, DESC_AF | DESC_PXN | DESC_UXN | DESC_ATTRINDX(1));\n+\n+ /* Set TTBR0_EL1 */\n+ write_sysreg(ttb_l1, ttbr0_el1);\n+\n+ /* Set MAIR_EL1 */\n+ write_sysreg(0xeeULL, mair_el1);\n+\n+ /* Set TCR_EL1 */\n+ uint64_t tcr = TCR_EL1_IPS_40BIT | TCR_EL1_TG0_4KB | TCR_EL1_ORGN0_WBWA | TCR_EL1_IRGN0_WBWA | TCR_EL1_T0SZ(25);\n+ write_sysreg(tcr, tcr_el1);\n+ isb();\n+\n+ /* Enable MMU via SCTLR_EL1 */\n+ uint64_t sctlr = read_sysreg(sctlr_el1);\n+ sctlr &= ~(1ULL << 1); /* Clear A (alignment check) */\n+ sctlr &= ~(1ULL << 19); /* Clear WXN */\n+ sctlr |= SCTLR_EL1_M | SCTLR_EL1_C | SCTLR_EL1_I | SCTLR_EL1_SA;\n+\n+ dsb(sy);\n+ write_sysreg(sctlr, sctlr_el1);\n+ isb();\n+}\ndiff --git a/tests/tcg/aarch64/Makefile.softmmu-target b/tests/tcg/aarch64/Makefile.softmmu-target\nindex c7f44803c73..5770ae1fb0c 100644\n--- a/tests/tcg/aarch64/Makefile.softmmu-target\n+++ b/tests/tcg/aarch64/Makefile.softmmu-target\n@@ -6,10 +6,10 @@ AARCH64_SRC=$(SRC_PATH)/tests/tcg/aarch64\n AARCH64_SYSTEM_SRC=$(AARCH64_SRC)/system\n AARCH64_SYSTEM_LIB=$(AARCH64_SRC)/system/lib\n \n-VPATH+=$(AARCH64_SYSTEM_SRC)\n+VPATH+=$(AARCH64_SYSTEM_SRC) $(AARCH64_SYSTEM_LIB)\n \n # These objects provide the basic boot code and helper functions for all tests\n-CRT_OBJS=boot.o\n+CRT_OBJS=boot.o pgtable.o\n \n AARCH64_TEST_C_SRCS=$(wildcard $(AARCH64_SYSTEM_SRC)/*.c)\n AARCH64_TEST_S_SRCS=$(AARCH64_SYSTEM_SRC)/mte.S\n@@ -37,9 +37,12 @@ config-cc.mak: Makefile\n # building head blobs\n .PRECIOUS: $(CRT_OBJS)\n \n-%.o: $(CRT_PATH)/%.S\n+%.o: %.S\n \t$(CC) $(CFLAGS) $(EXTRA_CFLAGS) -x assembler-with-cpp -Wa,--noexecstack -c $< -o $@\n \n+%.o: %.c\n+\t$(CC) $(CFLAGS) $(EXTRA_CFLAGS) -c $< -o $@\n+\n # Build and link the tests\n %: %.c $(LINK_SCRIPT) $(CRT_OBJS) $(MINILIB_OBJS)\n \t$(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS)\ndiff --git a/tests/tcg/aarch64/system/boot.S b/tests/tcg/aarch64/system/boot.S\nindex 8bfa4e4efc7..bee8d9372e7 100644\n--- a/tests/tcg/aarch64/system/boot.S\n+++ b/tests/tcg/aarch64/system/boot.S\n@@ -243,102 +243,7 @@ at_testel:\n \tmsr\tvbar_el1, x0\n \n \t/* Page table setup (identity mapping). */\n-\tadrp\tx0, ttb\n-\tadd\tx0, x0, :lo12:ttb\n-\tmsr\tttbr0_el1, x0\n-\n-\t/*\n-\t * Setup a flat address mapping page-tables. Stage one simply\n-\t * maps RAM to the first Gb. The stage2 tables have two 2mb\n-\t * translation block entries covering a series of adjacent\n-\t * 4k pages.\n-\t */\n-\n-\t/* Stage 1 entry: indexed by IA[38:30] */\n-\tadr\tx1, .\t\t\t\t/* phys address */\n-\tbic\tx1, x1, #(1 << 30) - 1\t\t/* 1GB alignment*/\n-\tadd\tx2, x0, x1, lsr #(30 - 3)\t/* offset in l1 page table */\n-\n-\t/* point to stage 2 table [47:12] */\n-\tadrp\tx0, ttb_stage2\n-\torr \tx1, x0, #3 \t\t\t/* ptr to stage 2 */\n-\tstr\tx1, [x2]\n-\n-\t/* Stage 2 entries: indexed by IA[29:21] */\n-\tldr\tx5, =(((1 << 9) - 1) << 21)\n-\n-\t/* First block: .text/RO/execute enabled */\n-\tadr\tx1, .\t\t\t\t/* phys address */\n-\tbic\tx1, x1, #(1 << 21) - 1\t\t/* 2mb block alignment\t*/\n-\tand\tx4, x1, x5\t\t\t/* IA[29:21] */\n-\tadd\tx2, x0, x4, lsr #(21 - 3)\t/* offset in l2 page table */\n-\tldr\tx3, =0x401\t\t\t/* attr(AF, block) */\n-\torr\tx1, x1, x3\n-\tstr\tx1, [x2]\t\t\t/* 1st 2mb (.text & rodata) */\n-\n-\t/* Second block: .data/RW/no execute */\n-\tadrp\tx1, .data\n-\tadd\tx1, x1, :lo12:.data\n-\tbic\tx1, x1, #(1 << 21) - 1\t\t/* 2mb block alignment */\n-\tand\tx4, x1, x5\t\t\t/* IA[29:21] */\n-\tadd\tx2, x0, x4, lsr #(21 - 3)\t/* offset in l2 page table */\n-\tldr\tx3, =(3 << 53) | 0x401\t\t/* attr(AF, NX, block) */\n-\torr\tx1, x1, x3\n-\tstr\tx1, [x2]\t\t\t/* 2nd 2mb (.data & .bss)*/\n-\n-\t/* Third block: at 'mte_page', set in kernel.ld */\n-\tadrp\tx1, mte_page\n-\tadd\tx1, x1, :lo12:mte_page\n-\tbic\tx1, x1, #(1 << 21) - 1\n-\tand \tx4, x1, x5\n-\tadd\tx2, x0, x4, lsr #(21 - 3)\n-\t/* attr(AF, NX, block, AttrIndx=Attr1) */\n-\tldr\tx3, =(3 << 53) | 0x401 | (1 << 2)\n-\torr\tx1, x1, x3\n-\tstr\tx1, [x2]\n-\n-\t/* Setup/enable the MMU. */\n-\n-\t/*\n-\t * TCR_EL1 - Translation Control Registers\n-\t *\n-\t * IPS[34:32] = 40-bit PA, 1TB\n-\t * TG0[14:15] = b00 => 4kb granuale\n-\t * ORGN0[11:10] = Outer: Normal, WB Read-Alloc No Write-Alloc Cacheable\n-\t * IRGN0[9:8] = Inner: Normal, WB Read-Alloc No Write-Alloc Cacheable\n-\t * T0SZ[5:0] = 2^(64 - 25)\n-\t *\n-\t * The size of T0SZ controls what the initial lookup level. It\n-\t * would be nice to start at level 2 but unfortunately for a\n-\t * flat-mapping on the virt machine we need to handle IA's\n-\t * with at least 1gb range to see RAM. So we start with a\n-\t * level 1 lookup.\n-\t */\n-\tldr\tx0, = (2 << 32) | 25 | (3 << 10) | (3 << 8)\n-\tmsr\ttcr_el1, x0\n-\n-\tmov\tx0, #0xee\t\t\t/* Inner/outer cacheable WB */\n-\tmsr\tmair_el1, x0\n-\tisb\n-\n-\t/*\n-\t * SCTLR_EL1 - System Control Register\n-\t *\n-\t * WXN[19] = 0 = no effect, Write does not imply XN (execute never)\n-\t * I[12] = Instruction cachability control\n-\t * SA[3] = SP alignment check\n-\t * C[2] = Data cachability control\n-\t * M[0] = 1, enable stage 1 address translation for EL0/1\n-\t */\n-\tmrs\tx0, sctlr_el1\n-\tldr\tx1, =0x100d\t\t\t/* bits I(12) SA(3) C(2) M(0) */\n-\tbic\tx0, x0, #(1 << 1)\t\t/* clear bit A(1) */\n-\tbic\tx0, x0, #(1 << 19)\t\t/* clear WXN */\n-\torr\tx0, x0, x1\t\t\t/* set bits */\n-\n-\tdsb\tsy\n-\tmsr\tsctlr_el1, x0\n-\tisb\n+\tbl\tsetup_pgtables\n \n \t/*\n \t * Enable FP/SVE registers. The standard C pre-amble will be\n@@ -392,18 +297,6 @@ cmdline:\n \t.space 128, 0\n \n \t.align\t12\n-\n-\t/* Translation table\n-\t * @4k granuale: 9 bit lookup, 512 entries\n-\t*/\n-ttb:\n-\t.space\t4096, 0\n-\n-\t.align\t12\n-ttb_stage2:\n-\t.space\t4096, 0\n-\n-\t.align\t12\n system_stack:\n \t.space 4096, 0\n system_stack_end:\ndiff --git a/tests/tcg/aarch64/system/kernel.ld b/tests/tcg/aarch64/system/kernel.ld\nindex aef043e31db..267ffcbe520 100644\n--- a/tests/tcg/aarch64/system/kernel.ld\n+++ b/tests/tcg/aarch64/system/kernel.ld\n@@ -13,10 +13,12 @@ MEMORY {\n \n SECTIONS {\n .text : {\n+ _text_start = .;\n *(.text)\n *(.rodata)\n } >TXT\n .data : {\n+ _data_start = .;\n *(.data)\n *(.bss)\n } >DAT\n@@ -25,6 +27,7 @@ SECTIONS {\n * Symbol 'mte_page' is used in boot.S to setup the PTE and in the mte.S\n * test as the address that the MTE instructions operate on.\n */\n+ _tag_start = .;\n mte_page = .;\n } >TAG\n /DISCARD/ : {\n","prefixes":["4/7"]}