{"id":2224552,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2224552/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/e31a0d39139aa5093a8e50a01bccb10a5e3f3142.1776438369.git.chao.liu.zevorn@gmail.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"","list_archive_url":null,"date":"2026-04-17T15:11:27","name":"[v6,3/5] hw/watchdog: add k230 watchdog initial support","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"a8ad05e4bbee62c69412cc58e8764fd94681147f","submitter":{"id":92265,"url":"http://patchwork.ozlabs.org/api/1.2/people/92265/?format=json","name":"Chao Liu","email":"chao.liu.zevorn@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/e31a0d39139aa5093a8e50a01bccb10a5e3f3142.1776438369.git.chao.liu.zevorn@gmail.com/mbox/","series":[{"id":500360,"url":"http://patchwork.ozlabs.org/api/1.2/series/500360/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500360","date":"2026-04-17T15:11:28","name":"Add support for K230 board","version":6,"mbox":"http://patchwork.ozlabs.org/series/500360/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2224552/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2224552/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=fE3vbUd+;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-ua1-x942.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Chao Liu \n\nAdd programmable Watchdog Timer (WDT) peripheral for K230 machine.\n\nSigned-off-by: Mig Yang \nSigned-off-by: Chao Liu \nReviewed-by: Daniel Henrique Barboza \n---\n MAINTAINERS | 2 +\n hw/riscv/Kconfig | 1 +\n hw/riscv/k230.c | 18 ++\n hw/watchdog/Kconfig | 4 +\n hw/watchdog/k230_wdt.c | 307 +++++++++++++++++++++++++++++++++\n hw/watchdog/meson.build | 1 +\n hw/watchdog/trace-events | 9 +\n include/hw/riscv/k230.h | 4 +\n include/hw/watchdog/k230_wdt.h | 132 ++++++++++++++\n 9 files changed, 478 insertions(+)\n create mode 100644 hw/watchdog/k230_wdt.c\n create mode 100644 include/hw/watchdog/k230_wdt.h","diff":"diff --git a/MAINTAINERS b/MAINTAINERS\nindex c429c63961..a2eecca155 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -1777,7 +1777,9 @@ K230 Machines\n M: Chao Liu \n S: Maintained\n F: hw/riscv/k230.c\n+F: hw/watchdog/k230_wdt.c\n F: include/hw/riscv/k230.h\n+F: include/hw/watchdog/k230_wdt.h\n \n RX Machines\n -----------\ndiff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig\nindex b1a7357866..5f8511cb92 100644\n--- a/hw/riscv/Kconfig\n+++ b/hw/riscv/Kconfig\n@@ -144,3 +144,4 @@ config K230\n select RISCV_IMSIC\n select SERIAL_MM\n select UNIMP\n+ select K230_WDT\ndiff --git a/hw/riscv/k230.c b/hw/riscv/k230.c\nindex 2537023a05..7df8a3298c 100644\n--- a/hw/riscv/k230.c\n+++ b/hw/riscv/k230.c\n@@ -113,6 +113,9 @@ static void k230_soc_init(Object *obj)\n RISCVHartArrayState *cpu0 = &s->c908_cpu;\n \n object_initialize_child(obj, \"c908-cpu\", cpu0, TYPE_RISCV_HART_ARRAY);\n+ object_initialize_child(obj, \"k230-wdt0\", &s->wdt[0], TYPE_K230_WDT);\n+ object_initialize_child(obj, \"k230-wdt1\", &s->wdt[1], TYPE_K230_WDT);\n+\n qdev_prop_set_uint32(DEVICE(cpu0), \"hartid-base\", 0);\n qdev_prop_set_string(DEVICE(cpu0), \"cpu-type\", TYPE_RISCV_CPU_THEAD_C908);\n qdev_prop_set_uint64(DEVICE(cpu0), \"resetvec\",\n@@ -190,6 +193,21 @@ static void k230_soc_realize(DeviceState *dev, Error **errp)\n qdev_get_gpio_in(DEVICE(s->c908_plic), K230_UART4_IRQ),\n 399193, serial_hd(4), DEVICE_LITTLE_ENDIAN);\n \n+ /* Watchdog */\n+ for (int i = 0; i < 2; i++) {\n+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) {\n+ return;\n+ }\n+ }\n+\n+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[0]), 0, memmap[K230_DEV_WDT0].base);\n+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[0]), 0,\n+ qdev_get_gpio_in(DEVICE(s->c908_plic), K230_WDT0_IRQ));\n+\n+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[1]), 0, memmap[K230_DEV_WDT1].base);\n+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[1]), 0,\n+ qdev_get_gpio_in(DEVICE(s->c908_plic), K230_WDT1_IRQ));\n+\n /* unimplemented devices */\n create_unimplemented_device(\"kpu.l2-cache\",\n memmap[K230_DEV_KPU_L2_CACHE].base,\ndiff --git a/hw/watchdog/Kconfig b/hw/watchdog/Kconfig\nindex 861fd00334..55f77c5c84 100644\n--- a/hw/watchdog/Kconfig\n+++ b/hw/watchdog/Kconfig\n@@ -18,6 +18,10 @@ config WDT_DIAG288\n config WDT_IMX2\n bool\n \n+config K230_WDT\n+ bool\n+ select PTIMER\n+\n config WDT_SBSA\n bool\n \ndiff --git a/hw/watchdog/k230_wdt.c b/hw/watchdog/k230_wdt.c\nnew file mode 100644\nindex 0000000000..66df0b738b\n--- /dev/null\n+++ b/hw/watchdog/k230_wdt.c\n@@ -0,0 +1,307 @@\n+/*\n+ * * K230 Watchdog Compatible with kendryte K230 SDK\n+ *\n+ * Copyright (c) 2025 Mig Yang \n+ * Copyright (c) 2025 Chao Liu \n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ *\n+ * Provides a board compatible with the kendryte K230 SDK\n+ *\n+ * Documentation: K230_Technical_Reference_Manual_V0.3.1_20241118.pdf\n+ *\n+ * For more information, see \n+ *\n+ * This program is free software; you can redistribute it and/or modify it\n+ * under the terms and conditions of the GNU General Public License,\n+ * version 2 or later, as published by the Free Software Foundation.\n+ *\n+ * This program is distributed in the hope it will be useful, but WITHOUT\n+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n+ * more details.\n+ *\n+ * You should have received a copy of the GNU General Public License along with\n+ * this program. If not, see .\n+ */\n+#include \"qemu/osdep.h\"\n+#include \"qemu/bitops.h\"\n+#include \"qemu/module.h\"\n+#include \"system/watchdog.h\"\n+#include \"migration/vmstate.h\"\n+#include \"hw/core/qdev-properties.h\"\n+#include \"hw/watchdog/k230_wdt.h\"\n+#include \"trace.h\"\n+\n+static void k230_wdt_timeout(void *opaque)\n+{\n+ K230WdtState *s = K230_WDT(opaque);\n+\n+ trace_k230_wdt_timeout();\n+\n+ /* Set interrupt status if in interrupt mode */\n+ if (s->cr & K230_WDT_CR_RMOD) {\n+ s->stat |= K230_WDT_STAT_INT;\n+ s->interrupt_pending = true;\n+ qemu_set_irq(s->irq, 1);\n+ trace_k230_wdt_interrupt();\n+ } else {\n+ /* Direct reset mode */\n+ trace_k230_wdt_reset();\n+ watchdog_perform_action();\n+ }\n+\n+ /* Restart counter */\n+ s->current_count = s->timeout_value;\n+ ptimer_set_count(s->timer, s->current_count);\n+ ptimer_run(s->timer, 1);\n+}\n+\n+static void k230_wdt_reset(DeviceState *dev)\n+{\n+ K230WdtState *s = K230_WDT(dev);\n+\n+ trace_k230_wdt_reset_device();\n+\n+ ptimer_transaction_begin(s->timer);\n+ ptimer_stop(s->timer);\n+ ptimer_transaction_commit(s->timer);\n+\n+ /* Reset registers to default values */\n+ s->cr = 0;\n+ s->torr = 0;\n+ s->ccvr = 0xFFFFFFFF;\n+ s->stat = 0;\n+ s->prot_level = 0x2;\n+\n+ s->interrupt_pending = false;\n+ s->enabled = false;\n+ s->timeout_value = 0;\n+ s->current_count = 0xFFFFFFFF;\n+}\n+\n+static uint64_t k230_wdt_read(void *opaque, hwaddr addr, unsigned int size)\n+{\n+ K230WdtState *s = K230_WDT(opaque);\n+ uint32_t value = 0;\n+\n+ switch (addr) {\n+ case K230_WDT_CR:\n+ value = s->cr;\n+ break;\n+ case K230_WDT_TORR:\n+ value = s->torr;\n+ break;\n+ case K230_WDT_CCVR:\n+ if (s->enabled) {\n+ value = ptimer_get_count(s->timer);\n+ } else {\n+ value = s->current_count;\n+ }\n+ break;\n+ case K230_WDT_STAT:\n+ value = s->stat;\n+ break;\n+ case K230_WDT_PROT_LEVEL:\n+ value = s->prot_level;\n+ break;\n+ case K230_WDT_COMP_PARAM_5:\n+ value = 0; /* Upper limit of Timeout Period parameters */\n+ break;\n+ case K230_WDT_COMP_PARAM_4:\n+ value = 0; /* Upper limit of Initial Timeout Period parameters */\n+ break;\n+ case K230_WDT_COMP_PARAM_3:\n+ value = 0; /* Derived from WDT_TOP_RST parameter */\n+ break;\n+ case K230_WDT_COMP_PARAM_2:\n+ value = 0xFFFFFFFF; /* Derived from WDT_RST_CNT parameter */\n+ break;\n+ case K230_WDT_COMP_PARAM_1:\n+ /* Component parameters */\n+ value = (32 << K230_WDT_CNT_WIDTH_SHIFT) | /* 32-bit counter */\n+ (0 << K230_WDT_DFLT_TOP_INIT_SHIFT) |\n+ (0 << K230_WDT_DFLT_TOP_SHIFT) |\n+ (K230_WDT_RPL_16_CYCLES << K230_WDT_DFLT_RPL_SHIFT) |\n+ (2 << K230_WDT_APB_DATA_WIDTH_SHIFT) | /* 32-bit APB */\n+ K230_WDT_USE_FIX_TOP; /* Use fixed timeout values */\n+ break;\n+ case K230_WDT_COMP_VERSION:\n+ value = K230_WDT_COMP_VERSION_VAL;\n+ break;\n+ case K230_WDT_COMP_TYPE:\n+ value = K230_WDT_COMP_TYPE_VAL;\n+ break;\n+ default:\n+ /* Other registers return 0 */\n+ break;\n+ }\n+\n+ trace_k230_wdt_read(addr, value);\n+ return value;\n+}\n+\n+static void k230_wdt_update_timer(K230WdtState *s)\n+{\n+ ptimer_transaction_begin(s->timer);\n+\n+ if (s->enabled && s->timeout_value > 0) {\n+ ptimer_set_count(s->timer, s->current_count);\n+ ptimer_run(s->timer, 1);\n+ } else {\n+ ptimer_stop(s->timer);\n+ }\n+\n+ ptimer_transaction_commit(s->timer);\n+}\n+\n+static uint32_t k230_wdt_calculate_timeout(uint32_t top_value)\n+{\n+ /* Calculate timeout based on TOP value */\n+ /* For fixed timeout mode: 2^(16 + top_value) */\n+ if (top_value <= 15) {\n+ return 1 << (16 + top_value);\n+ }\n+ return 1 << 31; /* Maximum value for 32-bit counter */\n+}\n+\n+static void k230_wdt_write(void *opaque, hwaddr addr,\n+ uint64_t value, unsigned int size)\n+{\n+ K230WdtState *s = K230_WDT(opaque);\n+\n+ trace_k230_wdt_write(addr, value);\n+\n+ switch (addr) {\n+ case K230_WDT_CR:\n+ s->cr = value & (K230_WDT_CR_RPL_MASK << K230_WDT_CR_RPL_SHIFT |\n+ K230_WDT_CR_RMOD | K230_WDT_CR_WDT_EN);\n+\n+ /* Update enabled state */\n+ s->enabled = (s->cr & K230_WDT_CR_WDT_EN) != 0;\n+\n+ /* Update timer */\n+ k230_wdt_update_timer(s);\n+ break;\n+\n+ case K230_WDT_TORR:\n+ s->torr = value & K230_WDT_TORR_TOP_MASK;\n+\n+ /* Calculate new timeout value */\n+ s->timeout_value = k230_wdt_calculate_timeout(s->torr);\n+ s->current_count = s->timeout_value;\n+\n+ /* Update timer if enabled */\n+ if (s->enabled) {\n+ k230_wdt_update_timer(s);\n+ }\n+ break;\n+\n+ case K230_WDT_CRR:\n+ /* Restart counter with magic value 0x76 */\n+ if ((value & 0xFF) == K230_WDT_CRR_RESTART) {\n+ trace_k230_wdt_restart();\n+ s->current_count = s->timeout_value;\n+\n+ /* Clear interrupt if pending */\n+ if (s->interrupt_pending) {\n+ s->stat &= ~K230_WDT_STAT_INT;\n+ s->interrupt_pending = false;\n+ qemu_set_irq(s->irq, 0);\n+ }\n+\n+ /* Update timer */\n+ k230_wdt_update_timer(s);\n+ }\n+ break;\n+\n+ case K230_WDT_EOI:\n+ /* Clear interrupt */\n+ s->stat &= ~K230_WDT_STAT_INT;\n+ s->interrupt_pending = false;\n+ qemu_set_irq(s->irq, 0);\n+ break;\n+\n+ case K230_WDT_PROT_LEVEL:\n+ s->prot_level = value & 0x7;\n+ break;\n+\n+ default:\n+ /* Read-only registers, ignore writes */\n+ break;\n+ }\n+}\n+\n+static const MemoryRegionOps k230_wdt_ops = {\n+ .read = k230_wdt_read,\n+ .write = k230_wdt_write,\n+ .endianness = DEVICE_NATIVE_ENDIAN,\n+ .impl = {\n+ .min_access_size = 4,\n+ .max_access_size = 4,\n+ .unaligned = false,\n+ },\n+};\n+\n+static const VMStateDescription vmstate_k230_wdt = {\n+ .name = \"k230.wdt\",\n+ .fields = (const VMStateField[]) {\n+ VMSTATE_PTIMER(timer, K230WdtState),\n+ VMSTATE_UINT32(cr, K230WdtState),\n+ VMSTATE_UINT32(torr, K230WdtState),\n+ VMSTATE_UINT32(ccvr, K230WdtState),\n+ VMSTATE_UINT32(stat, K230WdtState),\n+ VMSTATE_UINT32(prot_level, K230WdtState),\n+ VMSTATE_BOOL(interrupt_pending, K230WdtState),\n+ VMSTATE_BOOL(enabled, K230WdtState),\n+ VMSTATE_UINT32(timeout_value, K230WdtState),\n+ VMSTATE_UINT32(current_count, K230WdtState),\n+ VMSTATE_END_OF_LIST()\n+ }\n+};\n+\n+static void k230_wdt_realize(DeviceState *dev, Error **errp)\n+{\n+ K230WdtState *s = K230_WDT(dev);\n+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);\n+\n+ memory_region_init_io(&s->mmio, OBJECT(dev),\n+ &k230_wdt_ops, s,\n+ TYPE_K230_WDT,\n+ K230_WDT_MMIO_SIZE);\n+ sysbus_init_mmio(sbd, &s->mmio);\n+ sysbus_init_irq(sbd, &s->irq);\n+\n+ s->timer = ptimer_init(k230_wdt_timeout, s,\n+ PTIMER_POLICY_NO_IMMEDIATE_TRIGGER |\n+ PTIMER_POLICY_NO_IMMEDIATE_RELOAD |\n+ PTIMER_POLICY_NO_COUNTER_ROUND_DOWN);\n+\n+ ptimer_transaction_begin(s->timer);\n+ ptimer_set_freq(s->timer, K230_WDT_DEFAULT_FREQ);\n+ ptimer_transaction_commit(s->timer);\n+}\n+\n+static void k230_wdt_class_init(ObjectClass *klass, const void *data)\n+{\n+ DeviceClass *dc = DEVICE_CLASS(klass);\n+\n+ dc->realize = k230_wdt_realize;\n+ device_class_set_legacy_reset(dc, k230_wdt_reset);\n+ dc->vmsd = &vmstate_k230_wdt;\n+ dc->desc = \"K230 watchdog timer\";\n+ set_bit(DEVICE_CATEGORY_WATCHDOG, dc->categories);\n+}\n+\n+static const TypeInfo k230_wdt_info = {\n+ .name = TYPE_K230_WDT,\n+ .parent = TYPE_SYS_BUS_DEVICE,\n+ .instance_size = sizeof(K230WdtState),\n+ .class_init = k230_wdt_class_init,\n+};\n+\n+static void k230_wdt_register_type(void)\n+{\n+ type_register_static(&k230_wdt_info);\n+}\n+type_init(k230_wdt_register_type)\ndiff --git a/hw/watchdog/meson.build b/hw/watchdog/meson.build\nindex 15370565bd..5edae65a36 100644\n--- a/hw/watchdog/meson.build\n+++ b/hw/watchdog/meson.build\n@@ -6,5 +6,6 @@ system_ss.add(when: 'CONFIG_WDT_IB700', if_true: files('wdt_ib700.c'))\n system_ss.add(when: 'CONFIG_WDT_DIAG288', if_true: files('wdt_diag288.c'))\n system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('wdt_aspeed.c'))\n system_ss.add(when: 'CONFIG_WDT_IMX2', if_true: files('wdt_imx2.c'))\n+system_ss.add(when: 'CONFIG_K230_WDT', if_true: files('k230_wdt.c'))\n system_ss.add(when: 'CONFIG_WDT_SBSA', if_true: files('sbsa_gwdt.c'))\n specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('spapr_watchdog.c'))\ndiff --git a/hw/watchdog/trace-events b/hw/watchdog/trace-events\nindex ad3be1e9bd..d85b3ca769 100644\n--- a/hw/watchdog/trace-events\n+++ b/hw/watchdog/trace-events\n@@ -33,3 +33,12 @@ spapr_watchdog_expired(uint64_t num, unsigned action) \"num=%\" PRIu64 \" action=%u\n # watchdog.c\n watchdog_perform_action(unsigned int action) \"action=%u\"\n watchdog_set_action(unsigned int action) \"action=%u\"\n+\n+# k230_wdt.c\n+k230_wdt_read(uint64_t addr, uint32_t data) \"K230 WDT read: [0x%\" PRIx64 \"] -> 0x%\" PRIx32\n+k230_wdt_write(uint64_t addr, uint64_t data) \"K230 WDT write: [0x%\" PRIx64 \"] <- 0x%\" PRIx64\n+k230_wdt_timeout(void) \"K230 WDT timeout\"\n+k230_wdt_interrupt(void) \"K230 WDT interrupt\"\n+k230_wdt_reset(void) \"K230 WDT system reset\"\n+k230_wdt_restart(void) \"K230 WDT restart\"\n+k230_wdt_reset_device(void) \"K230 WDT device reset\"\ndiff --git a/include/hw/riscv/k230.h b/include/hw/riscv/k230.h\nindex 830175b756..84bd431bc9 100644\n--- a/include/hw/riscv/k230.h\n+++ b/include/hw/riscv/k230.h\n@@ -28,6 +28,7 @@\n \n #include \"hw/core/boards.h\"\n #include \"hw/riscv/riscv_hart.h\"\n+#include \"hw/watchdog/k230_wdt.h\"\n \n #define C908_CPU_HARTID (0)\n \n@@ -42,6 +43,7 @@ typedef struct K230SoCState {\n /*< public >*/\n RISCVHartArrayState c908_cpu; /* Small core */\n \n+ K230WdtState wdt[2];\n MemoryRegion sram;\n MemoryRegion bootrom;\n \n@@ -132,6 +134,8 @@ enum {\n K230_UART2_IRQ = 18,\n K230_UART3_IRQ = 19,\n K230_UART4_IRQ = 20,\n+ K230_WDT0_IRQ = 32,\n+ K230_WDT1_IRQ = 33,\n };\n \n /*\ndiff --git a/include/hw/watchdog/k230_wdt.h b/include/hw/watchdog/k230_wdt.h\nnew file mode 100644\nindex 0000000000..ec80567780\n--- /dev/null\n+++ b/include/hw/watchdog/k230_wdt.h\n@@ -0,0 +1,132 @@\n+/*\n+ * K230 Watchdog Timer\n+ *\n+ * Based on K230 technical documentation\n+ *\n+ * Copyright (c) 2025 Mig Yang \n+ * Copyright (c) 2025 Chao Liu \n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ *\n+ * This program is free software; you can redistribute it and/or modify it\n+ * under the terms and conditions of the GNU General Public License,\n+ * version 2 or later, as published by the Free Software Foundation.\n+ *\n+ * This program is distributed in the hope it will be useful, but WITHOUT\n+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n+ * more details.\n+ *\n+ * You should have received a copy of the GNU General Public License along with\n+ * this program. If not, see .\n+ */\n+\n+#ifndef K230_WDT_H\n+#define K230_WDT_H\n+\n+#include \"qemu/bitops.h\"\n+#include \"hw/core/sysbus.h\"\n+#include \"hw/core/irq.h\"\n+#include \"hw/core/ptimer.h\"\n+#include \"qom/object.h\"\n+\n+#define TYPE_K230_WDT \"riscv.k230.wdt\"\n+OBJECT_DECLARE_SIMPLE_TYPE(K230WdtState, K230_WDT)\n+\n+#define K230_WDT_DEFAULT_FREQ (32768)\n+\n+/* K230 Watchdog Register Map */\n+enum K230WdtRegisters {\n+ K230_WDT_CR = 0x00, /* Control Register */\n+ K230_WDT_TORR = 0x04, /* Timeout Range Register */\n+ K230_WDT_CCVR = 0x08, /* Current Counter Value Register */\n+ K230_WDT_CRR = 0x0c, /* Counter Restart Register */\n+ K230_WDT_STAT = 0x10, /* Interrupt Status Register */\n+ K230_WDT_EOI = 0x14, /* Interrupt Clear Register */\n+ K230_WDT_PROT_LEVEL = 0x1c, /* Protection Level Register */\n+ K230_WDT_COMP_PARAM_5 = 0xe4, /* Component Parameters Register 5 */\n+ K230_WDT_COMP_PARAM_4 = 0xe8, /* Component Parameters Register 4 */\n+ K230_WDT_COMP_PARAM_3 = 0xec, /* Component Parameters Register 3 */\n+ K230_WDT_COMP_PARAM_2 = 0xf0, /* Component Parameters Register 2 */\n+ K230_WDT_COMP_PARAM_1 = 0xf4, /* Component Parameters Register 1 */\n+ K230_WDT_COMP_VERSION = 0xf8, /* Component Version Register */\n+ K230_WDT_COMP_TYPE = 0xfc, /* Component Type Register */\n+};\n+\n+#define K230_WDT_MMIO_SIZE 0x100\n+\n+/* Control Register (WDT_CR) definitions */\n+#define K230_WDT_CR_RPL_MASK 0x7 /* Reset Pulse Length */\n+#define K230_WDT_CR_RPL_SHIFT 2\n+#define K230_WDT_CR_RMOD BIT(1) /* Response Mode */\n+#define K230_WDT_CR_WDT_EN BIT(0) /* Watchdog Enable */\n+\n+/* Reset Pulse Length values */\n+#define K230_WDT_RPL_2_CYCLES 0x0\n+#define K230_WDT_RPL_4_CYCLES 0x1\n+#define K230_WDT_RPL_8_CYCLES 0x2\n+#define K230_WDT_RPL_16_CYCLES 0x3\n+#define K230_WDT_RPL_32_CYCLES 0x4\n+#define K230_WDT_RPL_64_CYCLES 0x5\n+#define K230_WDT_RPL_128_CYCLES 0x6\n+#define K230_WDT_RPL_256_CYCLES 0x7\n+\n+/* Timeout Range Register (WDT_TORR) definitions */\n+#define K230_WDT_TORR_TOP_MASK 0xf /* Timeout Period */\n+\n+/* Interrupt Status Register (WDT_STAT) definitions */\n+#define K230_WDT_STAT_INT BIT(0) /* Interrupt Status */\n+\n+/* Counter Restart Register (WDT_CRR) magic value */\n+#define K230_WDT_CRR_RESTART 0x76 /* Restart command */\n+\n+/* Component Parameters Register 1 (WDT_COMP_PARAM_1) definitions */\n+#define K230_WDT_CNT_WIDTH_MASK 0x1f000000 /* Counter Width */\n+#define K230_WDT_CNT_WIDTH_SHIFT 24\n+#define K230_WDT_DFLT_TOP_INIT_MASK 0xf00000 /* Default Initial Timeout */\n+#define K230_WDT_DFLT_TOP_INIT_SHIFT 20\n+#define K230_WDT_DFLT_TOP_MASK 0xf0000 /* Default Timeout */\n+#define K230_WDT_DFLT_TOP_SHIFT 16\n+#define K230_WDT_DFLT_RPL_MASK 0x7 /* Default Reset Pulse Length */\n+#define K230_WDT_DFLT_RPL_SHIFT 10\n+#define K230_WDT_APB_DATA_WIDTH_MASK 0x3 /* APB Data Width */\n+#define K230_WDT_APB_DATA_WIDTH_SHIFT 8\n+#define K230_WDT_USE_FIX_TOP BIT(6) /* Use Fixed Timeout Values */\n+#define K230_WDT_HC_TOP BIT(5) /* Hard-coded Timeout */\n+#define K230_WDT_HC_RPL BIT(4) /* Hard-coded Reset Pulse Length */\n+#define K230_WDT_HC_RMOD BIT(3) /* Hard-coded Response Mode */\n+#define K230_WDT_DUAL_TOP BIT(2) /* Dual Timeout Period */\n+#define K230_WDT_DFLT_RMOD BIT(1) /* Default Response Mode */\n+#define K230_WDT_ALWAYS_EN BIT(0) /* Always Enabled */\n+\n+/* Component Type Register value */\n+#define K230_WDT_COMP_TYPE_VAL 0x44570120\n+\n+/* Component Version Register value */\n+#define K230_WDT_COMP_VERSION_VAL 0x3131302a /* \"110*\" */\n+\n+struct K230WdtState {\n+ /* */\n+ SysBusDevice parent_obj;\n+\n+ /*< public >*/\n+ MemoryRegion mmio;\n+ qemu_irq irq;\n+\n+ struct ptimer_state *timer;\n+\n+ /* Register state */\n+ uint32_t cr; /* Control Register */\n+ uint32_t torr; /* Timeout Range Register */\n+ uint32_t ccvr; /* Current Counter Value Register */\n+ uint32_t stat; /* Interrupt Status Register */\n+ uint32_t prot_level; /* Protection Level Register */\n+\n+ /* Internal state */\n+ bool interrupt_pending;\n+ bool enabled;\n+ uint32_t timeout_value;\n+ uint32_t current_count;\n+};\n+\n+#endif /* K230_WDT_H */\n","prefixes":["v6","3/5"]}