{"id":2224550,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2224550/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/e1a977e38c934a7f383530067230a6201b8ccc60.1776438369.git.chao.liu.zevorn@gmail.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"","list_archive_url":null,"date":"2026-04-17T15:11:25","name":"[v6,1/5] target/riscv: add thead-c908 cpu support","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"35d7374a0083b962cf687df7e7790fd685eab777","submitter":{"id":92265,"url":"http://patchwork.ozlabs.org/api/1.2/people/92265/?format=json","name":"Chao Liu","email":"chao.liu.zevorn@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/e1a977e38c934a7f383530067230a6201b8ccc60.1776438369.git.chao.liu.zevorn@gmail.com/mbox/","series":[{"id":500360,"url":"http://patchwork.ozlabs.org/api/1.2/series/500360/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500360","date":"2026-04-17T15:11:28","name":"Add support for K230 board","version":6,"mbox":"http://patchwork.ozlabs.org/series/500360/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2224550/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2224550/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 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Palmer Dabbelt ,\n Alistair Francis ,\n Weiwei Li ,\n Daniel Henrique Barboza ,\n Liu Zhiwei ,\n Paolo Bonzini ,\n Christoph Muellner ,\n Fabiano Rosas , Laurent Vivier ","Cc":"qemu-devel@nongnu.org, qemu-riscv@nongnu.org,\n Chao Liu ,\n Daniel Henrique Barboza ,\n Conor Dooley , Peng Jiang <3160104094@zju.edu.cn>","Subject":"[PATCH v6 1/5] target/riscv: add thead-c908 cpu support","Date":"Fri, 17 Apr 2026 23:11:25 +0800","Message-ID":"\n ","X-Mailer":"git-send-email 2.53.0","In-Reply-To":"","References":"","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2607:f8b0:4864:20::941;\n envelope-from=chao.liu.zevorn@gmail.com; helo=mail-ua1-x941.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Chao Liu \n\nThe C908 processor is based on the RV64GCB[V] instruction\nset, compatible to RVA22 Profile and implements the XIE\n(XuanTie Instruction Extension) technology.\n\nSigned-off-by: Chao Liu \nSuggested-by: LIU Zhiwei \nReviewed-by: Daniel Henrique Barboza \nReviewed-by: Conor Dooley \nReported-by: Peng Jiang <3160104094@zju.edu.cn>\n---\n target/riscv/cpu-qom.h | 2 +\n target/riscv/cpu.c | 51 ++++++\n target/riscv/th_csr.c | 380 ++++++++++++++++++++++++++++++++++++++++-\n 3 files changed, 432 insertions(+), 1 deletion(-)","diff":"diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h\nindex 30dcdcfaae..1a28f1369c 100644\n--- a/target/riscv/cpu-qom.h\n+++ b/target/riscv/cpu-qom.h\n@@ -52,6 +52,8 @@\n #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME(\"sifive-u34\")\n #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME(\"sifive-u54\")\n #define TYPE_RISCV_CPU_THEAD_C906 RISCV_CPU_TYPE_NAME(\"thead-c906\")\n+#define TYPE_RISCV_CPU_THEAD_C908 RISCV_CPU_TYPE_NAME(\"thead-c908\")\n+#define TYPE_RISCV_CPU_THEAD_C908V RISCV_CPU_TYPE_NAME(\"thead-c908v\")\n #define TYPE_RISCV_CPU_VEYRON_V1 RISCV_CPU_TYPE_NAME(\"veyron-v1\")\n #define TYPE_RISCV_CPU_TT_ASCALON RISCV_CPU_TYPE_NAME(\"tt-ascalon\")\n #define TYPE_RISCV_CPU_XIANGSHAN_NANHU RISCV_CPU_TYPE_NAME(\"xiangshan-nanhu\")\ndiff --git a/target/riscv/cpu.c b/target/riscv/cpu.c\nindex 72c6f4f0f1..870d0690fe 100644\n--- a/target/riscv/cpu.c\n+++ b/target/riscv/cpu.c\n@@ -3150,6 +3150,57 @@ static const TypeInfo riscv_cpu_type_infos[] = {\n #endif\n ),\n \n+ DEFINE_RISCV_CPU(TYPE_RISCV_CPU_THEAD_C908, TYPE_RISCV_VENDOR_CPU,\n+ .misa_mxl_max = MXL_RV64,\n+ .misa_ext = RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU,\n+ .priv_spec = PRIV_VERSION_1_12_0,\n+\n+ /* ISA extensions */\n+ .cfg.ext_xtheadba = true,\n+ .cfg.ext_xtheadbb = true,\n+ .cfg.ext_xtheadbs = true,\n+ .cfg.ext_xtheadcmo = true,\n+ .cfg.ext_xtheadcondmov = true,\n+ .cfg.ext_xtheadfmv = true,\n+ .cfg.ext_xtheadfmemidx = true,\n+ .cfg.ext_xtheadmac = true,\n+ .cfg.ext_xtheadmemidx = true,\n+ .cfg.ext_xtheadmempair = true,\n+ .cfg.ext_xtheadsync = true,\n+ .cfg.ext_smepmp = true,\n+ .cfg.ext_sscofpmf = true,\n+ .cfg.ext_sstc = true,\n+ .cfg.ext_svpbmt = true,\n+ .cfg.ext_svinval = true,\n+ .cfg.ext_svnapot = true,\n+ .cfg.ext_zba = true,\n+ .cfg.ext_zbb = true,\n+ .cfg.ext_zbc = true,\n+ .cfg.ext_zbs = true,\n+ .cfg.ext_zkt = true,\n+ .cfg.ext_zbkc = true,\n+ .cfg.ext_zicsr = true,\n+ .cfg.ext_zifencei = true,\n+ .cfg.ext_zihintpause = true,\n+ .cfg.ext_zicbom = true,\n+ .cfg.ext_zicboz = true,\n+\n+ .cfg.pmp = true,\n+ .cfg.mmu = true,\n+ .cfg.max_satp_mode = VM_1_10_SV48,\n+\n+ .cfg.marchid = 0x8d143000,\n+ .cfg.mvendorid = THEAD_VENDOR_ID,\n+#ifndef CONFIG_USER_ONLY\n+ .custom_csrs = th_csr_list,\n+#endif\n+ ),\n+\n+ DEFINE_RISCV_CPU(TYPE_RISCV_CPU_THEAD_C908V, TYPE_RISCV_CPU_THEAD_C908,\n+ .misa_ext = RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU | RVV,\n+ .vext_spec = VEXT_VERSION_1_00_0,\n+ ),\n+\n DEFINE_RISCV_CPU(TYPE_RISCV_CPU_TT_ASCALON, TYPE_RISCV_VENDOR_CPU,\n .misa_mxl_max = MXL_RV64,\n .misa_ext = RVG | RVC | RVS | RVU | RVH | RVV,\ndiff --git a/target/riscv/th_csr.c b/target/riscv/th_csr.c\nindex 49eb7bbab5..e19cab5414 100644\n--- a/target/riscv/th_csr.c\n+++ b/target/riscv/th_csr.c\n@@ -2,6 +2,9 @@\n * T-Head-specific CSRs.\n *\n * Copyright (c) 2024 VRULL GmbH\n+ * Copyright (c) 2025 Chao Liu \n+ *\n+ * For more information, see XuanTie-C908-UserManual_xrvm_20240530.pdf\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms and conditions of the GNU General Public License,\n@@ -20,13 +23,88 @@\n #include \"cpu.h\"\n #include \"cpu_vendorid.h\"\n \n-#define CSR_TH_SXSTATUS 0x5c0\n+/* Extended M-mode control registers of T-Head */\n+#define CSR_TH_MXSTATUS 0x7c0\n+#define CSR_TH_MHCR 0x7c1\n+#define CSR_TH_MCOR 0x7c2\n+#define CSR_TH_MCCR2 0x7c3\n+#define CSR_TH_MHINT 0x7c5\n+#define CSR_TH_MRVBR 0x7c7\n+#define CSR_TH_MCOUNTERWEN 0x7c9\n+#define CSR_TH_MCOUNTERINTEN 0x7ca\n+#define CSR_TH_MCOUNTEROF 0x7cb\n+#define CSR_TH_MCINS 0x7d2\n+#define CSR_TH_MCINDEX 0x7d3\n+#define CSR_TH_MCDATA0 0x7d4\n+#define CSR_TH_MCDATA1 0x7d5\n+#define CSR_TH_MSMPR 0x7f3\n+#define CSR_TH_CPUID 0xfc0\n+#define CSR_TH_MAPBADDR 0xfc1\n+\n+/* TH_MXSTATUS bits */\n+#define TH_MXSTATUS_UCME BIT(16)\n+#define TH_MXSTATUS_MAEE BIT(21)\n+#define TH_MXSTATUS_THEADISAEE BIT(22)\n+\n+/* Extended S-mode control registers of T-Head */\n+#define CSR_TH_SXSTATUS 0x5c0\n+#define CSR_TH_SHCR 0x5c1\n+#define CSR_TH_SCER2 0x5c2\n+#define CSR_TH_SCER 0x5c3\n+#define CSR_TH_SCOUNTERINTEN 0x5c4\n+#define CSR_TH_SCOUNTEROF 0x5c5\n+#define CSR_TH_SCYCLE 0x5e0\n+#define CSR_TH_SHPMCOUNTER3 0x5e3\n+#define CSR_TH_SHPMCOUNTER4 0x5e4\n+#define CSR_TH_SHPMCOUNTER5 0x5e5\n+#define CSR_TH_SHPMCOUNTER6 0x5e6\n+#define CSR_TH_SHPMCOUNTER7 0x5e7\n+#define CSR_TH_SHPMCOUNTER8 0x5e8\n+#define CSR_TH_SHPMCOUNTER9 0x5e9\n+#define CSR_TH_SHPMCOUNTER10 0x5ea\n+#define CSR_TH_SHPMCOUNTER11 0x5eb\n+#define CSR_TH_SHPMCOUNTER12 0x5ec\n+#define CSR_TH_SHPMCOUNTER13 0x5ed\n+#define CSR_TH_SHPMCOUNTER14 0x5ee\n+#define CSR_TH_SHPMCOUNTER15 0x5ef\n+#define CSR_TH_SHPMCOUNTER16 0x5f0\n+#define CSR_TH_SHPMCOUNTER17 0x5f1\n+#define CSR_TH_SHPMCOUNTER18 0x5f2\n+#define CSR_TH_SHPMCOUNTER19 0x5f3\n+#define CSR_TH_SHPMCOUNTER20 0x5f4\n+#define CSR_TH_SHPMCOUNTER21 0x5f5\n+#define CSR_TH_SHPMCOUNTER22 0x5f6\n+#define CSR_TH_SHPMCOUNTER23 0x5f7\n+#define CSR_TH_SHPMCOUNTER24 0x5f8\n+#define CSR_TH_SHPMCOUNTER25 0x5f9\n+#define CSR_TH_SHPMCOUNTER26 0x5fa\n+#define CSR_TH_SHPMCOUNTER27 0x5fb\n+#define CSR_TH_SHPMCOUNTER28 0x5fc\n+#define CSR_TH_SHPMCOUNTER29 0x5fd\n+#define CSR_TH_SHPMCOUNTER30 0x5fe\n+#define CSR_TH_SHPMCOUNTER31 0x5ff\n+#define CSR_TH_SMIR 0x9c0\n+#define CSR_TH_SMLO0 0x9c1\n+#define CSR_TH_SMEH 0x9c2\n+#define CSR_TH_SMCIR 0x9c3\n+\n+/* Extended U-mode control registers of T-Head */\n+#define CSR_TH_FXCR 0x800\n \n /* TH_SXSTATUS bits */\n #define TH_SXSTATUS_UCME BIT(16)\n #define TH_SXSTATUS_MAEE BIT(21)\n #define TH_SXSTATUS_THEADISAEE BIT(22)\n \n+static RISCVException mmode(CPURISCVState *env, int csrno)\n+{\n+ if (riscv_has_ext(env, RVM)) {\n+ return RISCV_EXCP_NONE;\n+ }\n+\n+ return RISCV_EXCP_ILLEGAL_INST;\n+}\n+\n static RISCVException smode(CPURISCVState *env, int csrno)\n {\n if (riscv_has_ext(env, RVS)) {\n@@ -36,11 +114,31 @@ static RISCVException smode(CPURISCVState *env, int csrno)\n return RISCV_EXCP_ILLEGAL_INST;\n }\n \n+static RISCVException any(CPURISCVState *env, int csrno)\n+{\n+ return RISCV_EXCP_NONE;\n+}\n+\n static bool test_thead_mvendorid(RISCVCPU *cpu)\n {\n return cpu->cfg.mvendorid == THEAD_VENDOR_ID;\n }\n \n+static RISCVException read_th_mxstatus(CPURISCVState *env, int csrno,\n+ target_ulong *val)\n+{\n+ /* We don't set MAEE here, because QEMU does not implement MAEE. */\n+ *val = TH_MXSTATUS_UCME | TH_MXSTATUS_THEADISAEE;\n+ return RISCV_EXCP_NONE;\n+}\n+\n+static RISCVException read_unimp_th_csr(CPURISCVState *env, int csrno,\n+ target_ulong *val)\n+{\n+ *val = 0;\n+ return RISCV_EXCP_NONE;\n+}\n+\n static RISCVException read_th_sxstatus(CPURISCVState *env, int csrno,\n target_ulong *val)\n {\n@@ -50,10 +148,290 @@ static RISCVException read_th_sxstatus(CPURISCVState *env, int csrno,\n }\n \n const RISCVCSR th_csr_list[] = {\n+ {\n+ .csrno = CSR_TH_MXSTATUS,\n+ .insertion_test = test_thead_mvendorid,\n+ .csr_ops = { \"th.mxstatus\", mmode, read_th_mxstatus }\n+ },\n+ {\n+ .csrno = CSR_TH_MHCR,\n+ .insertion_test = test_thead_mvendorid,\n+ .csr_ops = { \"th.mhcr\", mmode, read_unimp_th_csr }\n+ },\n+ {\n+ .csrno = CSR_TH_MCOR,\n+ .insertion_test = test_thead_mvendorid,\n+ .csr_ops = { \"th.mcor\", mmode, read_unimp_th_csr }\n+ },\n+ {\n+ .csrno = CSR_TH_MCCR2,\n+ .insertion_test = test_thead_mvendorid,\n+ .csr_ops = { \"th.mccr2\", mmode, read_unimp_th_csr }\n+ },\n+ {\n+ .csrno = CSR_TH_MHINT,\n+ .insertion_test = test_thead_mvendorid,\n+ .csr_ops = { \"th.mhint\", mmode, read_unimp_th_csr }\n+ },\n+ {\n+ .csrno = CSR_TH_MRVBR,\n+ .insertion_test = test_thead_mvendorid,\n+ .csr_ops = { \"th.mrvbr\", mmode, read_unimp_th_csr }\n+ },\n+ {\n+ .csrno = CSR_TH_MCOUNTERWEN,\n+ .insertion_test = test_thead_mvendorid,\n+ .csr_ops = { \"th.mcounterwen\", mmode, read_unimp_th_csr }\n+ },\n+ {\n+ .csrno = CSR_TH_MCOUNTERINTEN,\n+ .insertion_test = test_thead_mvendorid,\n+ .csr_ops = { \"th.mcounterinten\", mmode, read_unimp_th_csr }\n+ },\n+ {\n+ .csrno = CSR_TH_MCOUNTEROF,\n+ .insertion_test = test_thead_mvendorid,\n+ .csr_ops = { \"th.mcounterof\", mmode, read_unimp_th_csr }\n+ },\n+ {\n+ .csrno = CSR_TH_MCINS,\n+ .insertion_test = test_thead_mvendorid,\n+ .csr_ops = { \"th.mcins\", mmode, read_unimp_th_csr }\n+ },\n+ {\n+ .csrno = CSR_TH_MCINDEX,\n+ .insertion_test = test_thead_mvendorid,\n+ .csr_ops = { \"th.mcindex\", mmode, read_unimp_th_csr }\n+ },\n+ {\n+ .csrno = CSR_TH_MCDATA0,\n+ .insertion_test = test_thead_mvendorid,\n+ .csr_ops = { \"th.mcdata0\", mmode, read_unimp_th_csr }\n+ },\n+ {\n+ .csrno = CSR_TH_MCDATA1,\n+ .insertion_test = test_thead_mvendorid,\n+ .csr_ops = { \"th.mcdata1\", mmode, read_unimp_th_csr }\n+ },\n+ {\n+ .csrno = CSR_TH_MSMPR,\n+ .insertion_test = test_thead_mvendorid,\n+ .csr_ops = { \"th.msmpr\", mmode, read_unimp_th_csr }\n+ },\n+ {\n+ .csrno = CSR_TH_CPUID,\n+ .insertion_test = test_thead_mvendorid,\n+ .csr_ops = { \"th.cpuid\", mmode, read_unimp_th_csr }\n+ },\n+ {\n+ .csrno = CSR_TH_MAPBADDR,\n+ .insertion_test = test_thead_mvendorid,\n+ .csr_ops = { \"th.mapbaddr\", mmode, read_unimp_th_csr }\n+ },\n {\n .csrno = CSR_TH_SXSTATUS,\n .insertion_test = test_thead_mvendorid,\n .csr_ops = { \"th.sxstatus\", smode, read_th_sxstatus }\n },\n+ {\n+ .csrno = CSR_TH_SHCR,\n+ .insertion_test = test_thead_mvendorid,\n+ .csr_ops = { \"th.shcr\", smode, read_unimp_th_csr }\n+ },\n+ {\n+ .csrno = CSR_TH_SCER2,\n+ .insertion_test = test_thead_mvendorid,\n+ .csr_ops = { \"th.scer2\", smode, read_unimp_th_csr }\n+ },\n+ {\n+ .csrno = CSR_TH_SCER,\n+ .insertion_test = test_thead_mvendorid,\n+ .csr_ops = { \"th.scer\", smode, read_unimp_th_csr }\n+ },\n+ {\n+ .csrno = CSR_TH_SCOUNTERINTEN,\n+ .insertion_test = test_thead_mvendorid,\n+ .csr_ops = { \"th.scounterinten\", smode, read_unimp_th_csr }\n+ },\n+ {\n+ .csrno = CSR_TH_SCOUNTEROF,\n+ .insertion_test = test_thead_mvendorid,\n+ .csr_ops = { \"th.scounterof\", smode, read_unimp_th_csr }\n+ },\n+ {\n+ .csrno = CSR_TH_SCYCLE,\n+ .insertion_test = test_thead_mvendorid,\n+ .csr_ops = { \"th.scycle\", smode, read_unimp_th_csr }\n+ },\n+ {\n+ .csrno = CSR_TH_SHPMCOUNTER3,\n+ .insertion_test = test_thead_mvendorid,\n+ .csr_ops = { \"th.shpmcounter3\", smode, read_unimp_th_csr }\n+ },\n+ {\n+ .csrno = CSR_TH_SHPMCOUNTER4,\n+ .insertion_test = test_thead_mvendorid,\n+ .csr_ops = { \"th.shpmcounter4\", smode, read_unimp_th_csr }\n+ },\n+ {\n+ .csrno = CSR_TH_SHPMCOUNTER5,\n+ .insertion_test = test_thead_mvendorid,\n+ .csr_ops = { \"th.shpmcounter5\", smode, read_unimp_th_csr }\n+ },\n+ {\n+ .csrno = CSR_TH_SHPMCOUNTER6,\n+ .insertion_test = test_thead_mvendorid,\n+ .csr_ops = { \"th.shpmcounter6\", smode, read_unimp_th_csr }\n+ },\n+ {\n+ .csrno = CSR_TH_SHPMCOUNTER7,\n+ .insertion_test = test_thead_mvendorid,\n+ .csr_ops = { \"th.shpmcounter7\", smode, read_unimp_th_csr }\n+ },\n+ {\n+ .csrno = CSR_TH_SHPMCOUNTER8,\n+ .insertion_test = test_thead_mvendorid,\n+ .csr_ops = { \"th.shpmcounter8\", smode, read_unimp_th_csr }\n+ },\n+ {\n+ .csrno = CSR_TH_SHPMCOUNTER9,\n+ .insertion_test = test_thead_mvendorid,\n+ .csr_ops = { \"th.shpmcounter9\", smode, read_unimp_th_csr }\n+ },\n+ {\n+ .csrno = CSR_TH_SHPMCOUNTER10,\n+ .insertion_test = test_thead_mvendorid,\n+ .csr_ops = { \"th.shpmcounter10\", smode, read_unimp_th_csr }\n+ },\n+ {\n+ .csrno = CSR_TH_SHPMCOUNTER11,\n+ .insertion_test = test_thead_mvendorid,\n+ .csr_ops = { \"th.shpmcounter11\", smode, read_unimp_th_csr }\n+ },\n+ {\n+ .csrno = CSR_TH_SHPMCOUNTER12,\n+ .insertion_test = test_thead_mvendorid,\n+ .csr_ops = { \"th.shpmcounter12\", smode, read_unimp_th_csr }\n+ },\n+ {\n+ .csrno = CSR_TH_SHPMCOUNTER13,\n+ .insertion_test = test_thead_mvendorid,\n+ .csr_ops = { \"th.shpmcounter13\", smode, read_unimp_th_csr }\n+ },\n+ {\n+ .csrno = CSR_TH_SHPMCOUNTER14,\n+ .insertion_test = test_thead_mvendorid,\n+ .csr_ops = { \"th.shpmcounter14\", smode, read_unimp_th_csr }\n+ },\n+ {\n+ .csrno = CSR_TH_SHPMCOUNTER15,\n+ .insertion_test = test_thead_mvendorid,\n+ .csr_ops = { \"th.shpmcounter15\", smode, read_unimp_th_csr }\n+ },\n+ {\n+ .csrno = CSR_TH_SHPMCOUNTER16,\n+ .insertion_test = test_thead_mvendorid,\n+ .csr_ops = { \"th.shpmcounter16\", smode, read_unimp_th_csr }\n+ },\n+ {\n+ .csrno = CSR_TH_SHPMCOUNTER17,\n+ .insertion_test = test_thead_mvendorid,\n+ .csr_ops = { \"th.shpmcounter17\", smode, read_unimp_th_csr }\n+ },\n+ {\n+ .csrno = CSR_TH_SHPMCOUNTER18,\n+ .insertion_test = test_thead_mvendorid,\n+ .csr_ops = { \"th.shpmcounter18\", smode, read_unimp_th_csr }\n+ },\n+ {\n+ .csrno = CSR_TH_SHPMCOUNTER19,\n+ .insertion_test = test_thead_mvendorid,\n+ .csr_ops = { \"th.shpmcounter19\", smode, read_unimp_th_csr }\n+ },\n+ {\n+ .csrno = CSR_TH_SHPMCOUNTER20,\n+ .insertion_test = test_thead_mvendorid,\n+ .csr_ops = { \"th.shpmcounter20\", smode, read_unimp_th_csr }\n+ },\n+ {\n+ .csrno = CSR_TH_SHPMCOUNTER21,\n+ .insertion_test = test_thead_mvendorid,\n+ .csr_ops = { \"th.shpmcounter21\", smode, read_unimp_th_csr }\n+ },\n+ {\n+ .csrno = CSR_TH_SHPMCOUNTER22,\n+ .insertion_test = test_thead_mvendorid,\n+ .csr_ops = { \"th.shpmcounter22\", smode, read_unimp_th_csr }\n+ },\n+ {\n+ .csrno = CSR_TH_SHPMCOUNTER23,\n+ .insertion_test = test_thead_mvendorid,\n+ .csr_ops = { \"th.shpmcounter23\", smode, read_unimp_th_csr }\n+ },\n+ {\n+ .csrno = CSR_TH_SHPMCOUNTER24,\n+ .insertion_test = test_thead_mvendorid,\n+ .csr_ops = { \"th.shpmcounter24\", smode, read_unimp_th_csr }\n+ },\n+ {\n+ .csrno = CSR_TH_SHPMCOUNTER25,\n+ .insertion_test = test_thead_mvendorid,\n+ .csr_ops = { \"th.shpmcounter25\", smode, read_unimp_th_csr }\n+ },\n+ {\n+ .csrno = CSR_TH_SHPMCOUNTER26,\n+ .insertion_test = test_thead_mvendorid,\n+ .csr_ops = { \"th.shpmcounter26\", smode, read_unimp_th_csr }\n+ },\n+ {\n+ .csrno = CSR_TH_SHPMCOUNTER27,\n+ .insertion_test = test_thead_mvendorid,\n+ .csr_ops = { \"th.shpmcounter27\", smode, read_unimp_th_csr }\n+ },\n+ {\n+ .csrno = CSR_TH_SHPMCOUNTER28,\n+ .insertion_test = test_thead_mvendorid,\n+ .csr_ops = { \"th.shpmcounter28\", smode, read_unimp_th_csr }\n+ },\n+ {\n+ .csrno = CSR_TH_SHPMCOUNTER29,\n+ .insertion_test = test_thead_mvendorid,\n+ .csr_ops = { \"th.shpmcounter29\", smode, read_unimp_th_csr }\n+ },\n+ {\n+ .csrno = CSR_TH_SHPMCOUNTER30,\n+ .insertion_test = test_thead_mvendorid,\n+ .csr_ops = { \"th.shpmcounter30\", smode, read_unimp_th_csr }\n+ },\n+ {\n+ .csrno = CSR_TH_SHPMCOUNTER31,\n+ .insertion_test = test_thead_mvendorid,\n+ .csr_ops = { \"th.shpmcounter31\", smode, read_unimp_th_csr }\n+ },\n+ {\n+ .csrno = CSR_TH_SMIR,\n+ .insertion_test = test_thead_mvendorid,\n+ .csr_ops = { \"th.smir\", smode, read_unimp_th_csr }\n+ },\n+ {\n+ .csrno = CSR_TH_SMLO0,\n+ .insertion_test = test_thead_mvendorid,\n+ .csr_ops = { \"th.smlo0\", smode, read_unimp_th_csr }\n+ },\n+ {\n+ .csrno = CSR_TH_SMEH,\n+ .insertion_test = test_thead_mvendorid,\n+ .csr_ops = { \"th.smeh\", smode, read_unimp_th_csr }\n+ },\n+ {\n+ .csrno = CSR_TH_SMCIR,\n+ .insertion_test = test_thead_mvendorid,\n+ .csr_ops = { \"th.smcir\", smode, read_unimp_th_csr }\n+ },\n+ {\n+ .csrno = CSR_TH_FXCR,\n+ .insertion_test = test_thead_mvendorid,\n+ .csr_ops = { \"th.fxcr\", any, read_unimp_th_csr }\n+ },\n { }\n };\n","prefixes":["v6","1/5"]}