{"id":2224543,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2224543/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/fc0e1cb69ab0540a8e31a5f85522437e784c952e.1776437127.git.chao.liu.zevorn@gmail.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"","list_archive_url":null,"date":"2026-04-17T14:49:32","name":"[v10,2/2] tests/tcg/riscv64: Add test for vlsseg8e32 instruction","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"c98a6d4679c7caf47a970673c38c82e98e772ce2","submitter":{"id":92265,"url":"http://patchwork.ozlabs.org/api/1.2/people/92265/?format=json","name":"Chao Liu","email":"chao.liu.zevorn@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/fc0e1cb69ab0540a8e31a5f85522437e784c952e.1776437127.git.chao.liu.zevorn@gmail.com/mbox/","series":[{"id":500357,"url":"http://patchwork.ozlabs.org/api/1.2/series/500357/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500357","date":"2026-04-17T14:49:31","name":"Generate strided vector loads/stores with tcg nodes","version":10,"mbox":"http://patchwork.ozlabs.org/series/500357/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2224543/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2224543/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=cFpdaeNW;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-vk1-xa44.google.com","X-Spam_score_int":"-10","X-Spam_score":"-1.1","X-Spam_bar":"-","X-Spam_report":"(-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001,\n FREEMAIL_REPLY=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=no autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"This case, it copied 64 bytes from a0 to a1 with vlsseg8e32.\n\nSigned-off-by: Chao Liu \nSigned-off-by: Nicholas Piggin \nTested-by: Eric Biggers \n---\n tests/tcg/riscv64/Makefile.softmmu-target | 7 +-\n tests/tcg/riscv64/test-vlsseg8e32.S | 107 ++++++++++++++++++++++\n 2 files changed, 113 insertions(+), 1 deletion(-)\n create mode 100644 tests/tcg/riscv64/test-vlsseg8e32.S","diff":"diff --git a/tests/tcg/riscv64/Makefile.softmmu-target b/tests/tcg/riscv64/Makefile.softmmu-target\nindex 82be8a2c91..05c8f851e0 100644\n--- a/tests/tcg/riscv64/Makefile.softmmu-target\n+++ b/tests/tcg/riscv64/Makefile.softmmu-target\n@@ -7,7 +7,7 @@ VPATH += $(TEST_SRC)\n \n LINK_SCRIPT = $(TEST_SRC)/semihost.ld\n LDFLAGS = -T $(LINK_SCRIPT)\n-CFLAGS += -g -Og\n+CFLAGS += -march=rv64gcv -mabi=lp64d -g -Og\n \n %.o: %.S\n \t$(CC) $(CFLAGS) $< -Wa,--noexecstack -c -o $@\n@@ -41,5 +41,10 @@ comma:= ,\n run-test-crc32: test-crc32\n \t$(call run-test, $<, $(QEMU) -cpu rv64$(comma)xlrbr=true $(QEMU_OPTS)$<)\n \n+EXTRA_RUNS += run-vlsseg8e32\n+run-vlsseg8e32: QEMU_OPTS := -cpu rv64,v=true $(QEMU_OPTS)\n+run-vlsseg8e32: test-vlsseg8e32\n+\t$(call run-test, $<, $(QEMU) $(QEMU_OPTS)$<)\n+\n # We don't currently support the multiarch system tests\n undefine MULTIARCH_TESTS\ndiff --git a/tests/tcg/riscv64/test-vlsseg8e32.S b/tests/tcg/riscv64/test-vlsseg8e32.S\nnew file mode 100644\nindex 0000000000..bbc79d5e8d\n--- /dev/null\n+++ b/tests/tcg/riscv64/test-vlsseg8e32.S\n@@ -0,0 +1,107 @@\n+#\n+# QEMU RISC-V Vector Strided Load Instruction testcase\n+#\n+# Copyright (c) 2025 Chao Liu chao.liu@yeah.net\n+#\n+# SPDX-License-Identifier: GPL-2.0-or-later\n+#\n+\t.option\tnorvc\n+\n+\t.section .data\n+\t.align 4\n+source_data:\n+\t.asciz \"Test the vssseg8e32 insn by copy 64b and verifying correctness.\"\n+\t.equ source_len, 64\n+\n+\t.text\n+\t.global _start\n+_start:\n+\tlla\tt0, trap\n+\tcsrw\tmtvec, t0\n+\n+enable_rvv:\n+\n+\tli\tx15, 0x800000000024112d\n+\tcsrw\t0x301, x15\n+\tli\tx1, 0x2200\n+\tcsrr\tx2, mstatus\n+\tor\tx2, x2, x1\n+\tcsrw\tmstatus, x2\n+\n+rvv_test_func:\n+\tla\ta0, source_data\n+\tli\ta1, 0x80020000\n+\tvsetivli\tzero, 1, e32, m1, ta, ma\n+\tli\tt0, 64\n+\n+\tvlsseg8e32.v\tv0, (a0), t0\n+\taddi\ta0, a0, 32\n+\tvlsseg8e32.v\tv8, (a0), t0\n+\n+\tvssseg8e32.v\tv0, (a1), t0\n+\taddi\ta1, a1, 32\n+\tvssseg8e32.v\tv8, (a1), t0\n+\n+compare_start:\n+\tla\ta0, source_data\n+\tli\ta1, 0x80020000\n+\tli\tt0, 0\n+\tli\tt1, source_len\n+\n+compare_loop:\n+\t# when t0 >= len, compare end\n+\tbge\t t0, t1, compare_done\n+\n+\tlb\tt2, 0(a0)\n+\tlb\tt3, 0(a1)\n+\tbne\tt2, t3, compare_fail\n+\n+\taddi\ta0, a0, 1\n+\taddi\ta1, a1, 1\n+\taddi\tt0, t0, 1\n+\tj\tcompare_loop\n+\n+compare_done:\n+\t# compare ok, return 0\n+\tli\ta0, 0\n+\tj\t_exit\n+\n+compare_fail:\n+\t# compare failed, return 2\n+\tli\ta0, 2\n+\tj\t_exit\n+\n+trap:\n+\t# When an instruction traps, compare it to the insn in memory.\n+\tcsrr\tt0, mepc\n+\tcsrr\tt1, mtval\n+\tlwu\tt2, 0(t0)\n+\tbne\tt1, t2, fail\n+\n+\t# Skip the insn and continue.\n+\taddi\tt0, t0, 4\n+\tcsrw\tmepc, t0\n+\tmret\n+\n+fail:\n+\tli\ta0, 1\n+\n+# Exit code in a0\n+_exit:\n+\tlla\ta1, semiargs\n+\tli\tt0, 0x20026\t# ADP_Stopped_ApplicationExit\n+\tsd\tt0, 0(a1)\n+\tsd\ta0, 8(a1)\n+\tli\ta0, 0x20\t# TARGET_SYS_EXIT_EXTENDED\n+\n+\t# Semihosting call sequence\n+\t.balign\t16\n+\tslli\tzero, zero, 0x1f\n+\tebreak\n+\tsrai\tzero, zero, 0x7\n+\tj\t.\n+\n+\t.data\n+\t.balign\t16\n+semiargs:\n+\t.space\t16\n","prefixes":["v10","2/2"]}