{"id":2224538,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2224538/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417144905.178056-7-djordje.todorovic@htecgroup.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260417144905.178056-7-djordje.todorovic@htecgroup.com>","list_archive_url":null,"date":"2026-04-17T14:49:14","name":"[v8,6/7] target/riscv: Expose big-endian CPU property and add documentation","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"1981f5ee33435bed4f0c38f19125e2c3c6f560cb","submitter":{"id":90738,"url":"http://patchwork.ozlabs.org/api/1.2/people/90738/?format=json","name":"Djordje Todorovic","email":"Djordje.Todorovic@htecgroup.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417144905.178056-7-djordje.todorovic@htecgroup.com/mbox/","series":[{"id":500355,"url":"http://patchwork.ozlabs.org/api/1.2/series/500355/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500355","date":"2026-04-17T14:49:12","name":"Add RISC-V big-endian target support","version":8,"mbox":"http://patchwork.ozlabs.org/series/500355/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2224538/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2224538/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=htecgroup.com header.i=@htecgroup.com\n header.a=rsa-sha256 header.s=selector1 header.b=YqEBwtRX;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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When the property is set,\n+the CPU is reset with all three bits initialised to 1, so the guest starts\n+executing in big-endian data mode from the reset vector. The property is a\n+static, per-CPU hardware configuration option and is not meant to be toggled\n+at runtime.\n+\n+The property can be enabled from the command line, for example::\n+\n+ -cpu ,big-endian=on\n+\n+No upstream CPU model currently defaults to big-endian; the property is\n+provided so that big-endian-only RISC-V CPU variants can be modelled.\ndiff --git a/target/riscv/cpu.c b/target/riscv/cpu.c\nindex a32e4fd6d6..c39500cb3f 100644\n--- a/target/riscv/cpu.c\n+++ b/target/riscv/cpu.c\n@@ -2641,6 +2641,7 @@ RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[] = {\n \n static const Property riscv_cpu_properties[] = {\n DEFINE_PROP_BOOL(\"debug\", RISCVCPU, cfg.debug, true),\n+ DEFINE_PROP_BOOL(\"big-endian\", RISCVCPU, cfg.big_endian, false),\n \n {.name = \"pmu-mask\", .info = &prop_pmu_mask},\n {.name = \"pmu-num\", .info = &prop_pmu_num}, /* Deprecated */\n","prefixes":["v8","6/7"]}