{"id":2224536,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2224536/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/8ab885ce490cede31b8e9e7f6a67295c1aa353f7.1776437127.git.chao.liu.zevorn@gmail.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<8ab885ce490cede31b8e9e7f6a67295c1aa353f7.1776437127.git.chao.liu.zevorn@gmail.com>","list_archive_url":null,"date":"2026-04-17T14:49:31","name":"[v10,1/2] target/riscv: Use tcg nodes for strided vector ld/st generation","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"ea645c1abf8e8d851cf3177a61da46060e3c9fca","submitter":{"id":92265,"url":"http://patchwork.ozlabs.org/api/1.2/people/92265/?format=json","name":"Chao Liu","email":"chao.liu.zevorn@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/8ab885ce490cede31b8e9e7f6a67295c1aa353f7.1776437127.git.chao.liu.zevorn@gmail.com/mbox/","series":[{"id":500357,"url":"http://patchwork.ozlabs.org/api/1.2/series/500357/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500357","date":"2026-04-17T14:49:31","name":"Generate strided vector loads/stores with tcg nodes","version":10,"mbox":"http://patchwork.ozlabs.org/series/500357/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2224536/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2224536/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=RQ+vtk0S;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-vk1-xa41.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"This commit improves the performance of QEMU when emulating strided vector\nloads and stores by substituting the call for the helper function with the\ngeneration of equivalent TCG operations.\n\nPS:\n\nAn implementation is permitted to cause an illegal instruction if vstart\nis not 0 and it is set to a value that can not be produced implicitly by\nthe implementation, but memory accesses will generally always need to\ndeal with page faults.\n\nSo, if a strided vector memory access instruction has non-zero vstart,\ncheck it through vlse/vsse helpers function.\n\nSigned-off-by: Paolo Savini \nSigned-off-by: Chao Liu \nSigned-off-by: Nicholas Piggin \nTested-by: Eric Biggers \nReviewed-by: Daniel Henrique Barboza \n---\n target/riscv/insn_trans/trans_rvv.c.inc | 354 ++++++++++++++++++++++--\n 1 file changed, 337 insertions(+), 17 deletions(-)","diff":"diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc\nindex 5b72926b3c..4cf3643cbd 100644\n--- a/target/riscv/insn_trans/trans_rvv.c.inc\n+++ b/target/riscv/insn_trans/trans_rvv.c.inc\n@@ -16,6 +16,7 @@\n */\n #include \"tcg/tcg-op-gvec.h\"\n #include \"tcg/tcg-gvec-desc.h\"\n+#include \"tcg/tcg-temp-internal.h\"\n #include \"internals.h\"\n \n static inline bool is_overlapped(const int8_t astart, int8_t asize,\n@@ -872,15 +873,290 @@ static bool st_us_mask_check(DisasContext *s, arg_vsm_v *a, uint8_t eew)\n GEN_VEXT_TRANS(vlm_v, MO_8, vlm_v, ld_us_mask_op, ld_us_mask_check)\n GEN_VEXT_TRANS(vsm_v, MO_8, vsm_v, st_us_mask_op, st_us_mask_check)\n \n+/*\n+ * MAXSZ returns the maximum vector size can be operated in bytes,\n+ * which is used in GVEC IR when vl_eq_vlmax flag is set to true\n+ * to accelerate vector operation.\n+ */\n+static inline uint32_t MAXSZ(DisasContext *s)\n+{\n+ int max_sz = s->cfg_ptr->vlenb << 3;\n+ return max_sz >> (3 - s->lmul);\n+}\n+\n+static inline uint32_t get_log2(uint32_t a)\n+{\n+ assert(is_power_of_2(a));\n+ return ctz32(a);\n+}\n+\n+typedef void gen_tl_ldst(TCGv, TCGv_ptr, tcg_target_long);\n+\n+static void gen_ldst_vreg(DisasContext *s, TCGv_i64 dest_offs, TCGv_i64 addr,\n+ gen_tl_ldst *ld_fn, gen_tl_ldst *st_fn, bool is_load)\n+{\n+ MemOp atomicity = (s->sew == 0) ? MO_ATOM_NONE : MO_ATOM_IFALIGN_PAIR;\n+ TCGv_ptr dest_ptr = tcg_temp_new_ptr();\n+ TCGv_i64 vreg = tcg_temp_new_i64();\n+ tcg_gen_trunc_i64_ptr(dest_ptr, dest_offs);\n+\n+ if (is_load) {\n+ tcg_gen_qemu_ld_tl(vreg, addr, s->mem_idx, MO_LE | s->sew | atomicity);\n+ st_fn(vreg, dest_ptr, 0);\n+ } else {\n+ ld_fn(vreg, dest_ptr, 0);\n+ tcg_gen_qemu_st_tl(vreg, addr, s->mem_idx, MO_LE | s->sew | atomicity);\n+ }\n+ tcg_temp_free_ptr(dest_ptr);\n+ tcg_temp_free_i64(vreg);\n+}\n+\n+/*\n+ * Check whether the i bit of the mask is 0 or 1.\n+ *\n+ * static inline int vext_elem_mask(void *v0, int index)\n+ * {\n+ * int idx = index / 64;\n+ * int pos = index % 64;\n+ * return (((uint64_t *)v0)[idx] >> pos) & 1;\n+ * }\n+ *\n+ * And\n+ *\n+ * if (vext_elem_mask(v0, i) != 0) {\n+ * goto label;\n+ * }\n+ */\n+static void gen_check_vext_elem_mask(DisasContext *s, TCGLabel *label,\n+ TCGv_i64 mask_offs)\n+{\n+ TCGv_i64 temp = tcg_temp_new_i64();\n+ TCGv_ptr ptr = tcg_temp_new_ptr();\n+ TCGv_i64 elem = tcg_temp_new_i64();\n+\n+ tcg_gen_shri_tl(temp, mask_offs, 3);\n+ tcg_gen_trunc_i64_ptr(ptr, temp);\n+ tcg_gen_add_ptr(ptr, ptr, tcg_env);\n+\n+ tcg_gen_ld8u_i64(elem, ptr, 0);\n+ tcg_gen_andi_tl(temp, mask_offs, 7);\n+ tcg_gen_shr_tl(elem, elem, temp);\n+ tcg_gen_brcond_i64(TCG_COND_TSTNE, elem, tcg_constant_i64(1), label);\n+\n+ tcg_temp_free_i64(temp);\n+ tcg_temp_free_ptr(ptr);\n+ tcg_temp_free_i64(elem);\n+}\n+\n+static void gen_vext_set_elems_1s(TCGv dest, TCGv_i64 mask_offs, int sew,\n+ gen_tl_ldst *st_fn, bool is_load)\n+{\n+ if (is_load) {\n+ TCGv_ptr ptr = tcg_temp_new_ptr();\n+ tcg_gen_shli_tl(mask_offs, mask_offs, sew);\n+ tcg_gen_add_tl(mask_offs, mask_offs, dest);\n+ tcg_gen_trunc_i64_ptr(ptr, mask_offs);\n+ st_fn(tcg_constant_tl(-1), ptr, 0);\n+ tcg_temp_free_ptr(ptr);\n+ }\n+}\n+\n+/*\n+ * Simulate the strided load/store main loop:\n+ *\n+ * for (i = env->vstart; i < env->vl; env->vstart = ++i) {\n+ * k = 0;\n+ * while (k < nf) {\n+ * if (!vm && !vext_elem_mask(v0, i)) {\n+ * vext_set_elems_1s(vd, vma, (i + k * max_elems) * esz,\n+ * (i + k * max_elems + 1) * esz);\n+ * k++;\n+ * continue;\n+ * }\n+ * target_ulong addr = base + stride * i + (k << log2_esz);\n+ * ldst(env, adjust_addr(env, addr), i + k * max_elems, vd, ra);\n+ * k++;\n+ * }\n+ * }\n+ */\n+static void gen_ldst_stride_main_loop(DisasContext *s, TCGv dest, uint32_t rs1,\n+ uint32_t rs2, uint32_t vm, uint32_t nf,\n+ gen_tl_ldst *ld_fn, gen_tl_ldst *st_fn,\n+ bool is_load)\n+{\n+ TCGv_i64 addr = tcg_temp_new_i64();\n+ TCGv base = get_gpr(s, rs1, EXT_NONE);\n+ TCGv stride = get_gpr(s, rs2, EXT_NONE);\n+\n+ TCGv i = tcg_temp_new();\n+ TCGv i_esz = tcg_temp_new();\n+ TCGv k = tcg_temp_new();\n+ TCGv k_esz = tcg_temp_new();\n+ TCGv k_max = tcg_temp_new();\n+ TCGv_i64 mask_offs = tcg_temp_new_i64();\n+ TCGv_i64 dest_offs = tcg_temp_new_i64();\n+ TCGv_i64 stride_offs = tcg_temp_new_i64();\n+\n+ uint32_t max_elems = MAXSZ(s) >> s->sew;\n+\n+ TCGLabel *start = gen_new_label();\n+ TCGLabel *end = gen_new_label();\n+ TCGLabel *start_k = gen_new_label();\n+ TCGLabel *inc_k = gen_new_label();\n+ TCGLabel *end_k = gen_new_label();\n+\n+ /* Start of outer loop. */\n+ tcg_gen_mov_tl(i, cpu_vstart);\n+ gen_set_label(start);\n+ tcg_gen_brcond_tl(TCG_COND_GE, i, cpu_vl, end);\n+ tcg_gen_shli_tl(i_esz, i, s->sew);\n+\n+ /* Start of inner loop. */\n+ tcg_gen_movi_tl(k, 0);\n+ gen_set_label(start_k);\n+ tcg_gen_brcond_tl(TCG_COND_GE, k, tcg_constant_tl(nf), end_k);\n+\n+ /*\n+ * If we are in mask agnostic regime and the operation is not unmasked we\n+ * set the inactive elements to 1.\n+ */\n+ if (!vm && s->vma) {\n+ TCGLabel *active_element = gen_new_label();\n+ /* (i + k * max_elems) * esz */\n+ tcg_gen_shli_tl(mask_offs, k, get_log2(max_elems << s->sew));\n+ tcg_gen_add_tl(mask_offs, mask_offs, i_esz);\n+\n+ /*\n+ * Check whether the i bit of the mask is 0 or 1.\n+ * If it is 0, set masked-off elements;\n+ * otherwise, directly load/store the vector register.\n+ */\n+ gen_check_vext_elem_mask(s, active_element, mask_offs);\n+\n+ /*\n+ * Set masked-off elements in the destination vector register to 1s.\n+ * Store instructions simply skip this bit as memory ops access memory\n+ * only for active elements.\n+ */\n+ gen_vext_set_elems_1s(dest, mask_offs, s->sew, st_fn, is_load);\n+\n+ tcg_gen_br(inc_k);\n+ gen_set_label(active_element);\n+ }\n+\n+ /*\n+ * The element is active, calculate the address with stride:\n+ * target_ulong addr = base + stride * i + (k << log2_esz);\n+ */\n+ tcg_gen_mul_tl(stride_offs, stride, i);\n+ tcg_gen_shli_tl(k_esz, k, s->sew);\n+ tcg_gen_add_tl(stride_offs, stride_offs, k_esz);\n+ tcg_gen_add_tl(addr, base, stride_offs);\n+\n+ /* Calculate the offset in the dst/src vector register. */\n+ tcg_gen_shli_tl(k_max, k, get_log2(max_elems));\n+ tcg_gen_add_tl(dest_offs, i, k_max);\n+ tcg_gen_shli_tl(dest_offs, dest_offs, s->sew);\n+ tcg_gen_add_tl(dest_offs, dest_offs, dest);\n+\n+ /* Load/Store vector register. */\n+ gen_ldst_vreg(s, dest_offs, addr, ld_fn, st_fn, is_load);\n+\n+ /*\n+ * We don't execute the load/store above if the element was inactive.\n+ * We jump instead directly to incrementing k and continuing the loop.\n+ */\n+ if (!vm && s->vma) {\n+ gen_set_label(inc_k);\n+ }\n+ tcg_gen_addi_tl(k, k, 1);\n+ tcg_gen_br(start_k);\n+\n+ /* End of the inner loop. */\n+ gen_set_label(end_k);\n+\n+ tcg_gen_addi_tl(i, i, 1);\n+ tcg_gen_mov_tl(cpu_vstart, i);\n+ tcg_gen_br(start);\n+\n+ /* End of the outer loop. */\n+ gen_set_label(end);\n+\n+ return;\n+}\n+\n+/*\n+ * Set the tail bytes of the strided loads/stores to 1:\n+ *\n+ * for (k = 0; k < nf; ++k) {\n+ * cnt = (k * max_elems + vl) * esz;\n+ * tot = (k * max_elems + max_elems) * esz;\n+ * for (i = cnt; i < tot; i += esz) {\n+ * store_1s(-1, vd[vl+i]);\n+ * }\n+ * }\n+ */\n+static void gen_ldst_stride_tail_loop(DisasContext *s, TCGv dest, uint32_t nf,\n+ gen_tl_ldst *st_fn)\n+{\n+ TCGv i = tcg_temp_new();\n+ TCGv k = tcg_temp_new();\n+ TCGv tail_cnt = tcg_temp_new();\n+ TCGv tail_tot = tcg_temp_new();\n+ TCGv tail_addr = tcg_temp_new();\n+\n+ TCGLabel *start = gen_new_label();\n+ TCGLabel *end = gen_new_label();\n+ TCGLabel *start_i = gen_new_label();\n+ TCGLabel *end_i = gen_new_label();\n+\n+ uint32_t max_elems_b = MAXSZ(s);\n+ uint32_t esz = 1 << s->sew;\n+\n+ /* Start of the outer loop. */\n+ tcg_gen_movi_tl(k, 0);\n+ tcg_gen_shli_tl(tail_cnt, cpu_vl, s->sew);\n+ tcg_gen_movi_tl(tail_tot, max_elems_b);\n+ tcg_gen_add_tl(tail_addr, dest, tail_cnt);\n+ gen_set_label(start);\n+ tcg_gen_brcond_tl(TCG_COND_GE, k, tcg_constant_tl(nf), end);\n+\n+ /* Start of the inner loop. */\n+ tcg_gen_mov_tl(i, tail_cnt);\n+ gen_set_label(start_i);\n+ tcg_gen_brcond_tl(TCG_COND_GE, i, tail_tot, end_i);\n+\n+ /* store_1s(-1, vd[vl+i]); */\n+ st_fn(tcg_constant_tl(-1), (TCGv_ptr)tail_addr, 0);\n+ tcg_gen_addi_tl(tail_addr, tail_addr, esz);\n+ tcg_gen_addi_tl(i, i, esz);\n+ tcg_gen_br(start_i);\n+\n+ /* End of the inner loop. */\n+ gen_set_label(end_i);\n+\n+ /* Update the counts */\n+ tcg_gen_addi_tl(tail_cnt, tail_cnt, max_elems_b);\n+ tcg_gen_addi_tl(tail_tot, tail_cnt, max_elems_b);\n+ tcg_gen_addi_tl(k, k, 1);\n+ tcg_gen_br(start);\n+\n+ /* End of the outer loop. */\n+ gen_set_label(end);\n+\n+ return;\n+}\n+\n /*\n *** stride load and store\n */\n typedef void gen_helper_ldst_stride(TCGv_ptr, TCGv_ptr, TCGv,\n TCGv, TCGv_env, TCGv_i32);\n \n-static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2,\n- uint32_t data, gen_helper_ldst_stride *fn,\n- DisasContext *s)\n+static\n+bool gen_call_helper_ldst_stride(uint32_t vd, uint32_t rs1, uint32_t rs2,\n+ uint32_t data, gen_helper_ldst_stride *fn,\n+ DisasContext *s)\n {\n TCGv_ptr dest, mask;\n TCGv base, stride;\n@@ -904,11 +1180,66 @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2,\n return true;\n }\n \n+static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2,\n+ uint32_t data, gen_helper_ldst_stride *fn,\n+ DisasContext *s, bool is_load)\n+{\n+ if (!s->vstart_eq_zero) {\n+ /* vstart != 0 helper slowpath */\n+ return gen_call_helper_ldst_stride(vd, rs1, rs2, data, fn, s);\n+ }\n+\n+ TCGv dest = tcg_temp_new();\n+\n+ uint32_t nf = FIELD_EX32(data, VDATA, NF);\n+ uint32_t vm = FIELD_EX32(data, VDATA, VM);\n+\n+ /* Destination register and mask register */\n+ tcg_gen_addi_tl(dest, (TCGv)tcg_env, vreg_ofs(s, vd));\n+\n+ /*\n+ * Select the appropriate load/store to retrieve data from the vector\n+ * register given a specific sew.\n+ */\n+ static gen_tl_ldst * const ld_fns[4] = {\n+ tcg_gen_ld8u_tl, tcg_gen_ld16u_tl,\n+ tcg_gen_ld32u_tl, tcg_gen_ld_tl\n+ };\n+\n+ static gen_tl_ldst * const st_fns[4] = {\n+ tcg_gen_st8_tl, tcg_gen_st16_tl,\n+ tcg_gen_st32_tl, tcg_gen_st_tl\n+ };\n+\n+ gen_tl_ldst *ld_fn = ld_fns[s->sew];\n+ gen_tl_ldst *st_fn = st_fns[s->sew];\n+\n+ if (ld_fn == NULL || st_fn == NULL) {\n+ return false;\n+ }\n+\n+ mark_vs_dirty(s);\n+\n+ gen_ldst_stride_main_loop(s, dest, rs1, rs2, vm, nf, ld_fn, st_fn, is_load);\n+\n+ tcg_gen_movi_tl(cpu_vstart, 0);\n+\n+ /*\n+ * Set the tail bytes to 1 if tail agnostic:\n+ */\n+ if (s->vta != 0 && is_load) {\n+ gen_ldst_stride_tail_loop(s, dest, nf, st_fn);\n+ }\n+\n+ finalize_rvv_inst(s);\n+ return true;\n+}\n+\n static bool ld_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t eew)\n {\n uint32_t data = 0;\n gen_helper_ldst_stride *fn;\n- static gen_helper_ldst_stride * const fns[4] = {\n+ static gen_helper_ldst_stride *const fns[4] = {\n gen_helper_vlse8_v, gen_helper_vlse16_v,\n gen_helper_vlse32_v, gen_helper_vlse64_v\n };\n@@ -924,7 +1255,7 @@ static bool ld_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t eew)\n data = FIELD_DP32(data, VDATA, NF, a->nf);\n data = FIELD_DP32(data, VDATA, VTA, s->vta);\n data = FIELD_DP32(data, VDATA, VMA, s->vma);\n- return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s);\n+ return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s, true);\n }\n \n static bool ld_stride_check(DisasContext *s, arg_rnfvm* a, uint8_t eew)\n@@ -958,7 +1289,7 @@ static bool st_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t eew)\n return false;\n }\n \n- return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s);\n+ return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s, false);\n }\n \n static bool st_stride_check(DisasContext *s, arg_rnfvm* a, uint8_t eew)\n@@ -1281,17 +1612,6 @@ GEN_LDST_WHOLE_TRANS(vs8r_v, int8_t, 8, false)\n *** Vector Integer Arithmetic Instructions\n */\n \n-/*\n- * MAXSZ returns the maximum vector size can be operated in bytes,\n- * which is used in GVEC IR when vl_eq_vlmax flag is set to true\n- * to accelerate vector operation.\n- */\n-static inline uint32_t MAXSZ(DisasContext *s)\n-{\n- int max_sz = s->cfg_ptr->vlenb * 8;\n- return max_sz >> (3 - s->lmul);\n-}\n-\n static bool opivv_check(DisasContext *s, arg_rmrr *a)\n {\n return require_rvv(s) &&\n","prefixes":["v10","1/2"]}