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i >= 0; i--) {\n+\t\tif (!plat_iocu_usable(cluster, i))\n+\t\t\tnum_iocus_usable--;\n+\t}\n+\tgd->arch.num_iocus_usable += num_iocus_usable;\n+\n+\t/* If the cluster has no usable IOCUs there's nothing to do */\n+\tif (num_iocus_usable == 0) {\n+\t\tif (cluster != local_cluster)\n+\t\t\tpower_down_cluster(cluster);\n+\n+\t\treturn 0;\n+\t}\n+\n+\t/* If the IOCUs are in the local cluster we're good to go already */\n+\tif (cluster == local_cluster)\n+\t\treturn 0;\n+\n+\t/* Ensure that the cluster's L2 cache is initialised */\n+\treturn init_cluster_l2(cluster);\n+}\n+\n+int mips_cm_init_iocus(void)\n+{\n+\tDECLARE_GLOBAL_DATA_PTR;\n+\tunsigned int cluster;\n+\tint err;\n+\n+\tfor (cluster = 0; cluster < mips_cm_num_clusters(); cluster++) {\n+\t\terr = init_cluster_iocus(cluster);\n+\t\tif (err) {\n+\t\t\tgd->arch.num_iocus_usable = err;\n+\t\t\treturn 0;\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\ndiff --git a/arch/riscv/cpu/p8700/cm.c b/arch/riscv/cpu/p8700/cm.c\nnew file mode 100644\nindex 00000000000..ce7485c564d\n--- /dev/null\n+++ b/arch/riscv/cpu/p8700/cm.c\n@@ -0,0 +1,92 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+/*\n+ * MIPS Coherence Manager (CM) Support\n+ *\n+ * Copyright (c) 2016 Imagination Technologies Ltd.\n+ */\n+\n+#include \n+#include \n+#include \n+\n+static void mips_cpc_init(void)\n+{\n+}\n+\n+__weak const struct mmio_region *get_mmio_regions(void)\n+{\n+\treturn NULL;\n+}\n+\n+static void p8700_setup_mmio_limits(void)\n+{\n+\tvoid __iomem *gcrs = mips_cm_base();\n+\tconst struct mmio_region *rgn = get_mmio_regions();\n+\tunsigned int num_clusters = mips_cm_num_clusters();\n+\tunsigned int limit = MIPS_CM_MMIO_LIMIT / num_clusters;\n+\tunsigned int i, reg_off;\n+\n+\tif (!rgn)\n+\t\treturn;\n+\n+\tif (num_clusters != 1) {\n+\t\t// FIXME! Need to support multiple clusters.\n+\t\treturn;\n+\t}\n+\n+\treg_off = GCR_MMIO0_BOTTOM;\n+\n+\tfor (i = 0; rgn[i].addr_high; i++) {\n+\t\t__raw_writeq(rgn[i].addr_high & GCR_MMIO0_TOP_ADDR,\n+\t\t\t gcrs + reg_off + (GCR_MMIO0_TOP - GCR_MMIO0_BOTTOM));\n+\n+\t\t__raw_writeq((rgn[i].addr_low & GCR_MMIO0_BOTTOM_ADDR) |\n+\t\t\t (rgn[i].port << GCR_MMIO0_BOTTOM_PORT_SHIFT) |\n+\t\t\t (rgn[i].enable ? GCR_MMIO0_BOTTOM_ENABLE : 0),\n+\t\t\t gcrs + reg_off);\n+\t\treg_off += GCR_MMIO1_BOTTOM - GCR_MMIO0_BOTTOM;\n+\t}\n+\n+\t__raw_writel(limit, gcrs + GCR_MMIO_REQ_LIMIT);\n+}\n+\n+int power_up_cluster(unsigned int cluster)\n+{\n+\treturn 0;\n+}\n+\n+int power_down_cluster(unsigned int cluster)\n+{\n+\treturn 0;\n+}\n+\n+int init_cluster_l2(unsigned int cluster)\n+{\n+\treturn 0;\n+}\n+\n+int mips_cm_init(void)\n+{\n+\tint err;\n+\n+\tmips_cpc_init();\n+\n+\terr = mips_cm_init_iocus();\n+\tif (err)\n+\t\treturn err;\n+\n+\tp8700_setup_mmio_limits();\n+\n+\treturn 0;\n+}\n+\n+int arch_cpu_init(void)\n+{\n+\tint err;\n+\n+\terr = mips_cm_init();\n+\tif (err)\n+\t\treturn err;\n+\n+\treturn 0;\n+}\ndiff --git a/arch/riscv/cpu/p8700/p8700.c b/arch/riscv/cpu/p8700/p8700.c\nindex 41d5547c511..802ec65ffb2 100644\n--- a/arch/riscv/cpu/p8700/p8700.c\n+++ b/arch/riscv/cpu/p8700/p8700.c\n@@ -10,3 +10,5 @@\n __weak void wait_ddr_calib(void) { }\n \n __weak void setup_pcie_dma_map(void) { }\n+\n+__weak bool dma_is_coherent(void) { return false; }\ndiff --git a/arch/riscv/include/asm/arch-p8700/cm.h b/arch/riscv/include/asm/arch-p8700/cm.h\nnew file mode 100644\nindex 00000000000..ab5ea7385b2\n--- /dev/null\n+++ b/arch/riscv/include/asm/arch-p8700/cm.h\n@@ -0,0 +1,61 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (C) 2021, Chao-ying Fu \n+ */\n+\n+#ifndef __P8700_CM_H__\n+#define __P8700_CM_H__\n+\n+#include \n+\n+struct mmio_region {\n+\tphys_addr_t addr_low;\n+\tphys_addr_t addr_high;\n+\tunsigned int port : 4;\n+\tunsigned int enable : 1;\n+};\n+\n+const struct mmio_region *get_mmio_regions(void);\n+\n+void setup_redirect(unsigned int cluster, unsigned int core,\n+\t\t unsigned int vp, unsigned int block);\n+\n+int mips_cm_init_iocus(void);\n+\n+int power_up_cluster(unsigned int cluster);\n+int power_down_cluster(unsigned int cluster);\n+int init_cluster_l2(unsigned int cluster);\n+\n+static inline void *mips_cm_base(void)\n+{\n+\treturn (void *)CM_BASE;\n+}\n+\n+static inline void *mips_cpc_base(void)\n+{\n+\treturn (void *)CPC_BASE;\n+}\n+\n+static inline unsigned int mips_cm_num_clusters(void)\n+{\n+\tu32 cfg;\n+\n+\tcfg = __raw_readl(mips_cm_base() + GCR_CONFIG);\n+\tcfg >>= GCR_CONFIG_NUMCLUSTERS_SHIFT;\n+\tcfg &= GCR_CONFIG_NUMCLUSTERS_MASK;\n+\n+\treturn cfg;\n+}\n+\n+static inline unsigned int mips_cluster_id(void)\n+{\n+\tu32 temp;\n+\n+\tasm volatile(\"csrr %0, mhartid\" : \"=r\"(temp));\n+\ttemp >>= MHARTID_CLUSTER_SHIFT;\n+\ttemp &= MHARTID_CLUSTER_MASK;\n+\n+\treturn temp;\n+}\n+\n+#endif /* __P8700_CM_H__ */\ndiff --git a/arch/riscv/include/asm/arch-p8700/p8700.h b/arch/riscv/include/asm/arch-p8700/p8700.h\nindex d6cc125d76a..98ce5ba3ffb 100644\n--- a/arch/riscv/include/asm/arch-p8700/p8700.h\n+++ b/arch/riscv/include/asm/arch-p8700/p8700.h\n@@ -65,6 +65,10 @@\n #define CM_BASE\t\t\tCONFIG_RISCV_CM_BASE\n #define CPC_BASE\t\t(CM_BASE + 0x8000)\n \n+/* Block offsets */\n+#define GCR_OFF_GLOBAL\t\t0x0000\n+#define GCR_OFF_LOCAL\t\t0x2000\n+\n /* CPC Block offsets */\n #define CPC_OFF_LOCAL\t\t0x2000\n \n@@ -75,6 +79,33 @@\n #define CPC_Cx_CMD\t\t0x0000\n #define CPC_Cx_CMD_RESET\t0x4\n \n+/* GCR_CONFIG */\n+#define GCR_CONFIG\t\t\t\t\t\t0x0000\n+#define GCR_REV\t\t\t\t\t\t\t0x0030\n+#define GCR_CONFIG_NUMCLUSTERS_SHIFT\t23\n+#define GCR_CONFIG_NUMCLUSTERS_MASK\t 0x7f\n+#define GCR_CONFIG_NUMIOCU_SHIFT\t 8\n+#define GCR_CONFIG_NUMIOCU_MASK\t\t 0xf\n+#define GCR_CONFIG_NUMCORES_SHIFT\t 0\n+#define GCR_CONFIG_NUMCORES_MASK\t 0xff\n+\n+/* GCR_REV CM versions */\n+#define GCR_REV_CM3\t\t\t0x0800\n+#define GCR_REV_CM3_5\t\t0x0900\n+\n+#define GCR_MMIO_REQ_LIMIT\t\t\t\t0x06f8\n+#define GCR_MMIO0_BOTTOM\t\t\t\t0x0700\n+#define GCR_MMIO0_BOTTOM_ADDR\t\t\t(0xffffffffull << 16)\n+#define GCR_MMIO0_BOTTOM_PORT_SHIFT\t\t2\n+#define GCR_MMIO0_BOTTOM_PORT\t\t\t(0xf << 2)\n+#define GCR_MMIO0_BOTTOM_DISABLE_LIMIT\t(0x1 << 1)\n+#define GCR_MMIO0_BOTTOM_ENABLE\t\t\t(0x1 << 0)\n+#define GCR_MMIO0_TOP\t\t\t\t\t0x0708\n+#define GCR_MMIO0_TOP_ADDR\t\t\t\t(0xffffffffull << 16)\n+#define GCR_MMIO1_BOTTOM\t\t\t\t0x0710\n+\n+#define MIPS_CM_MMIO_LIMIT\t4\n+\n #define P8700_GCR_C0_COH_EN\t0x20f8\n #define P8700_GCR_C1_COH_EN\t0x21f8\n #define P8700_GCR_C2_COH_EN\t0x22f8\n@@ -97,5 +128,6 @@\n \n void wait_ddr_calib(void);\n void setup_pcie_dma_map(void);\n+bool dma_is_coherent(void);\n \n #endif /* __P8700_H__ */\ndiff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h\nindex 33f2b5ec5c8..198eacd1e07 100644\n--- a/arch/riscv/include/asm/global_data.h\n+++ b/arch/riscv/include/asm/global_data.h\n@@ -44,6 +44,10 @@ struct arch_global_data {\n \tulong smbios_start;\t\t/* Start address of SMBIOS table */\n #endif\n \tstruct resume_data *resume;\n+#if CONFIG_IS_ENABLED(P8700_RISCV)\n+\tint num_iocus;\n+\tint num_iocus_usable;\n+#endif\n };\n \n #include \ndiff --git a/board/mips/boston-riscv/Makefile b/board/mips/boston-riscv/Makefile\nindex 0615c677d23..c67c001d4e6 100644\n--- a/board/mips/boston-riscv/Makefile\n+++ b/board/mips/boston-riscv/Makefile\n@@ -4,5 +4,6 @@\n \n obj-y += boston-riscv.o\n obj-y += checkboard.o\n+obj-y += iocu.o\n obj-y += lowlevel_init.o\n obj-y += reset.o\ndiff --git a/board/mips/boston-riscv/boston-riscv.c b/board/mips/boston-riscv/boston-riscv.c\nindex f3fd2ec8348..4af918c8c81 100644\n--- a/board/mips/boston-riscv/boston-riscv.c\n+++ b/board/mips/boston-riscv/boston-riscv.c\n@@ -46,3 +46,14 @@ void setup_pcie_dma_map(void)\n \twritel(0x00, (void __iomem *)BOSTON_PLAT_NOCPCIE1ADDR);\n \twritel(0x00, (void __iomem *)BOSTON_PLAT_NOCPCIE2ADDR);\n }\n+\n+bool dma_is_coherent(void)\n+{\n+\tu32 pcie0_off = readl((void __iomem *)BOSTON_PLAT_NOCPCIE0ADDR);\n+\tu32 pcie1_off = readl((void __iomem *)BOSTON_PLAT_NOCPCIE1ADDR);\n+\tu32 pcie2_off = readl((void __iomem *)BOSTON_PLAT_NOCPCIE2ADDR);\n+\n+\treturn pcie0_off == BOSTON_IOCU_NOC_OFFSET &&\n+\t pcie1_off == BOSTON_IOCU_NOC_OFFSET &&\n+\t pcie2_off == BOSTON_IOCU_NOC_OFFSET;\n+}\ndiff --git a/board/mips/boston-riscv/iocu.c b/board/mips/boston-riscv/iocu.c\nnew file mode 100644\nindex 00000000000..807f09804a3\n--- /dev/null\n+++ b/board/mips/boston-riscv/iocu.c\n@@ -0,0 +1,102 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+/*\n+ * Copyright (c) 2016 Imagination Technologies Ltd.\n+ */\n+\n+#include \"boston-regs.h\"\n+#include \n+#include \n+#include \n+#include \n+#include \n+\n+static const struct mmio_region mmio_regions[] = {\n+\t{ 0x10000000, 0x160f0000, .enable = 1 },\n+\t{ 0x17ff0000, 0x17ff0000, .enable = 1 },\n+\t{ 0 },\n+};\n+\n+const struct mmio_region *get_mmio_regions(void)\n+{\n+\treturn mmio_regions;\n+}\n+\n+static int set_io_coherent(bool coherent)\n+{\n+\tDECLARE_GLOBAL_DATA_PTR;\n+\n+\tif (!coherent) {\n+\t\tprintf(\"I/O: Non-Coherent (Forced by environment)\\n\");\n+\t\tgoto noncoherent;\n+\t}\n+\n+\tif (gd->arch.num_iocus_usable < 0) {\n+\t\tprintf(\"I/O: Non-Coherent (IOCU init error %d)\\n\",\n+\t\t gd->arch.num_iocus_usable);\n+\t\tgoto noncoherent;\n+\t}\n+\n+\tif (gd->arch.num_iocus == 0) {\n+\t\tprintf(\"I/O: Non-Coherent (No IOCU)\\n\");\n+\t\tgoto noncoherent;\n+\t}\n+\n+\tif (gd->arch.num_iocus_usable == 0) {\n+\t\tprintf(\"I/O: Non-Coherent (IOCU not connected)\\n\");\n+\t\tgoto noncoherent;\n+\t}\n+\n+\t/*\n+\t * We have some number of connected IOCUs. Map all PCIe DMA access to\n+\t * hit the IOCU by offsetting the addresses as they pass from the PCIe\n+\t * controller to the NoC.\n+\t */\n+\twritel(0x10, (u32 *)BOSTON_PLAT_NOCPCIE0ADDR);\n+\twritel(0x10, (u32 *)BOSTON_PLAT_NOCPCIE1ADDR);\n+\twritel(0x10, (u32 *)BOSTON_PLAT_NOCPCIE2ADDR);\n+\n+\tprintf(\"I/O: Coherent\\n\");\n+\treturn 0;\n+\n+noncoherent:\n+\t/* Map all PCIe DMA access to its default, non-IOCU, target */\n+\twritel(0x00, (u32 *)BOSTON_PLAT_NOCPCIE0ADDR);\n+\twritel(0x00, (u32 *)BOSTON_PLAT_NOCPCIE1ADDR);\n+\twritel(0x00, (u32 *)BOSTON_PLAT_NOCPCIE2ADDR);\n+\t\n+\treturn 0;\n+}\n+\n+static int on_io_coherent(const char *name, const char *value,\n+\t\t\t enum env_op op, int flags)\n+{\n+\tswitch (op) {\n+\tcase env_op_create:\n+\tcase env_op_overwrite:\n+\t\tif (!strcmp(value, \"0\")) {\n+\t\t\tset_io_coherent(false);\n+\t\t} else if (!strcmp(value, \"1\")) {\n+\t\t\tset_io_coherent(true);\n+\t\t} else {\n+\t\t\tprintf(\"### io.coherent must equal 0 or 1\\n\");\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\treturn 0;\n+\n+\tcase env_op_delete:\n+\t\tset_io_coherent(true);\n+\t\treturn 0;\n+\n+\tdefault:\n+\t\treturn 0;\n+\t}\n+}\n+\n+U_BOOT_ENV_CALLBACK(io_coherent, on_io_coherent);\n+\n+static int p8700_misc_init_f(void)\n+{\n+\treturn set_io_coherent(env_get_yesno(\"io.coherent\") != 0);\n+}\n+\n+EVENT_SPY_SIMPLE(EVT_MISC_INIT_F, p8700_misc_init_f);\n","prefixes":["v7","7/7"]}