{"id":2224375,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2224375/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417105618.3621-2-magnuskulke@linux.microsoft.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260417105618.3621-2-magnuskulke@linux.microsoft.com>","list_archive_url":null,"date":"2026-04-17T10:55:45","name":"[01/34] target/i386/mshv: use arch_load/store_reg fns","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"c72844e8a864a6a71d4ac608b01bac81fbb00970","submitter":{"id":90753,"url":"http://patchwork.ozlabs.org/api/1.2/people/90753/?format=json","name":"Magnus Kulke","email":"magnuskulke@linux.microsoft.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417105618.3621-2-magnuskulke@linux.microsoft.com/mbox/","series":[{"id":500310,"url":"http://patchwork.ozlabs.org/api/1.2/series/500310/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500310","date":"2026-04-17T10:55:44","name":"Add migration support to the MSHV accelerator","version":1,"mbox":"http://patchwork.ozlabs.org/series/500310/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2224375/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2224375/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=linux.microsoft.com header.i=@linux.microsoft.com\n header.a=rsa-sha256 header.s=default header.b=eKKkOVDm;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fxsKB1Fnhz1yD3\n\tfor ; Fri, 17 Apr 2026 20:57:16 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wDgsC-0000Jr-K0; Fri, 17 Apr 2026 06:56:32 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wDgsB-0000Iv-8u\n for qemu-devel@nongnu.org; Fri, 17 Apr 2026 06:56:31 -0400","from linux.microsoft.com ([13.77.154.182])\n by eggs.gnu.org with esmtp (Exim 4.90_1)\n (envelope-from ) id 1wDgs9-0001Hn-BD\n for qemu-devel@nongnu.org; Fri, 17 Apr 2026 06:56:31 -0400","from DESKTOP-TUU1E5L.fritz.box (p5086d620.dip0.t-ipconnect.de\n [80.134.214.32])\n by linux.microsoft.com (Postfix) with ESMTPSA id 50C5020B7129;\n Fri, 17 Apr 2026 03:56:25 -0700 (PDT)"],"DKIM-Filter":"OpenDKIM Filter v2.11.0 linux.microsoft.com 50C5020B7129","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com;\n s=default; t=1776423388;\n bh=Vlb84NjCXw4NOONm0D1TCpsCilPuQF2CzdK3RJxUGA0=;\n h=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n b=eKKkOVDmtfcnC1Z5Fbt7GMN3ytR5hULbR6Jo6QJN+JdawvFnWIz1SlcyKdqbk5umG\n 5MgnRyd7bYryZGX27OcNjC4szU50dUIwEuSyQZbk6BN3NxYpdzQP8Tgnk8iPxPXsx0\n YXaLAz37RH0kTEj89RyBFrZeJJOaNBcs5eDaJceA=","From":"Magnus Kulke ","To":"qemu-devel@nongnu.org","Cc":"kvm@vger.kernel.org, Magnus Kulke ,\n Wei Liu , \"Michael S. Tsirkin\" ,\n\t=?utf-8?q?C=C3=A9dric_Le_Goater?= ,\n Zhao Liu ,\n Richard Henderson ,\n Paolo Bonzini , Wei Liu ,\n Magnus Kulke ,\n Alex Williamson ,\n Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?=\n\t=?utf-8?q?aud=C3=A9?= ,\n Marcelo Tosatti ","Subject":"[PATCH 01/34] target/i386/mshv: use arch_load/store_reg fns","Date":"Fri, 17 Apr 2026 12:55:45 +0200","Message-Id":"<20260417105618.3621-2-magnuskulke@linux.microsoft.com>","X-Mailer":"git-send-email 2.34.1","In-Reply-To":"<20260417105618.3621-1-magnuskulke@linux.microsoft.com>","References":"<20260417105618.3621-1-magnuskulke@linux.microsoft.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=13.77.154.182;\n envelope-from=magnuskulke@linux.microsoft.com; helo=linux.microsoft.com","X-Spam_score_int":"-42","X-Spam_score":"-4.3","X-Spam_bar":"----","X-Spam_report":"(-4.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, RCVD_IN_DNSWL_MED=-2.3,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001,\n SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Improved consistency around the naming of load/store register fn's. this\nis required since we want to roundtrip more registers in a migration\nthan what's currently required for MMIO emulation.\n\nSigned-off-by: Magnus Kulke \n---\n accel/mshv/mshv-all.c | 2 +-\n include/system/mshv_int.h | 6 ++---\n target/i386/mshv/mshv-cpu.c | 52 ++++++++++++++-----------------------\n 3 files changed, 23 insertions(+), 37 deletions(-)","diff":"diff --git a/accel/mshv/mshv-all.c b/accel/mshv/mshv-all.c\nindex d4cc7f5371..7c0eb68a5b 100644\n--- a/accel/mshv/mshv-all.c\n+++ b/accel/mshv/mshv-all.c\n@@ -650,7 +650,7 @@ static void mshv_cpu_synchronize_pre_loadvm(CPUState *cpu)\n static void do_mshv_cpu_synchronize(CPUState *cpu, run_on_cpu_data arg)\n {\n if (!cpu->accel->dirty) {\n- int ret = mshv_load_regs(cpu);\n+ int ret = mshv_arch_load_regs(cpu);\n if (ret < 0) {\n error_report(\"Failed to load registers for vcpu %d\",\n cpu->cpu_index);\ndiff --git a/include/system/mshv_int.h b/include/system/mshv_int.h\nindex 35386c422f..a142dd241a 100644\n--- a/include/system/mshv_int.h\n+++ b/include/system/mshv_int.h\n@@ -82,11 +82,9 @@ void mshv_init_mmio_emu(void);\n int mshv_create_vcpu(int vm_fd, uint8_t vp_index, int *cpu_fd);\n void mshv_remove_vcpu(int vm_fd, int cpu_fd);\n int mshv_configure_vcpu(const CPUState *cpu, const MshvFPU *fpu, uint64_t xcr0);\n-int mshv_get_standard_regs(CPUState *cpu);\n-int mshv_get_special_regs(CPUState *cpu);\n int mshv_run_vcpu(int vm_fd, CPUState *cpu, hv_message *msg, MshvVmExit *exit);\n-int mshv_load_regs(CPUState *cpu);\n-int mshv_store_regs(CPUState *cpu);\n+int mshv_arch_load_regs(CPUState *cpu);\n+int mshv_arch_store_regs(CPUState *cpu);\n int mshv_set_generic_regs(const CPUState *cpu, const hv_register_assoc *assocs,\n size_t n_regs);\n int mshv_arch_put_registers(const CPUState *cpu);\ndiff --git a/target/i386/mshv/mshv-cpu.c b/target/i386/mshv/mshv-cpu.c\nindex 2bc978deb2..9456e75277 100644\n--- a/target/i386/mshv/mshv-cpu.c\n+++ b/target/i386/mshv/mshv-cpu.c\n@@ -107,6 +107,8 @@ static enum hv_register_name FPU_REGISTER_NAMES[26] = {\n HV_X64_REGISTER_XMM_CONTROL_STATUS,\n };\n \n+static int set_special_regs(const CPUState *cpu);\n+\n static int translate_gva(const CPUState *cpu, uint64_t gva, uint64_t *gpa,\n uint64_t flags)\n {\n@@ -285,7 +287,7 @@ static int set_standard_regs(const CPUState *cpu)\n return 0;\n }\n \n-int mshv_store_regs(CPUState *cpu)\n+int mshv_arch_store_regs(CPUState *cpu)\n {\n int ret;\n \n@@ -295,6 +297,12 @@ int mshv_store_regs(CPUState *cpu)\n return -1;\n }\n \n+ ret = set_special_regs(cpu);\n+ if (ret < 0) {\n+ error_report(\"Failed to store speical registers\");\n+ return ret;\n+ }\n+\n return 0;\n }\n \n@@ -323,7 +331,7 @@ static void populate_standard_regs(const hv_register_assoc *assocs,\n rflags_to_lflags(env);\n }\n \n-int mshv_get_standard_regs(CPUState *cpu)\n+static int get_standard_regs(CPUState *cpu)\n {\n struct hv_register_assoc assocs[ARRAY_SIZE(STANDARD_REGISTER_NAMES)];\n int ret;\n@@ -401,8 +409,7 @@ static void populate_special_regs(const hv_register_assoc *assocs,\n cpu_set_apic_base(x86cpu->apic_state, assocs[16].value.reg64);\n }\n \n-\n-int mshv_get_special_regs(CPUState *cpu)\n+static int get_special_regs(CPUState *cpu)\n {\n struct hv_register_assoc assocs[ARRAY_SIZE(SPECIAL_REGISTER_NAMES)];\n int ret;\n@@ -422,17 +429,17 @@ int mshv_get_special_regs(CPUState *cpu)\n return 0;\n }\n \n-int mshv_load_regs(CPUState *cpu)\n+int mshv_arch_load_regs(CPUState *cpu)\n {\n int ret;\n \n- ret = mshv_get_standard_regs(cpu);\n+ ret = get_standard_regs(cpu);\n if (ret < 0) {\n error_report(\"Failed to load standard registers\");\n return -1;\n }\n \n- ret = mshv_get_special_regs(cpu);\n+ ret = get_special_regs(cpu);\n if (ret < 0) {\n error_report(\"Failed to load special registers\");\n return -1;\n@@ -1103,16 +1110,16 @@ static int emulate_instruction(CPUState *cpu,\n int ret;\n x86_insn_stream stream = { .bytes = insn_bytes, .len = insn_len };\n \n- ret = mshv_load_regs(cpu);\n+ ret = mshv_arch_load_regs(cpu);\n if (ret < 0) {\n- error_report(\"failed to load registers\");\n+ error_report(\"Failed to load registers\");\n return -1;\n }\n \n decode_instruction_stream(env, &decode, &stream);\n exec_instruction(env, &decode);\n \n- ret = mshv_store_regs(cpu);\n+ ret = mshv_arch_store_regs(cpu);\n if (ret < 0) {\n error_report(\"failed to store registers\");\n return -1;\n@@ -1291,25 +1298,6 @@ static int handle_pio_non_str(const CPUState *cpu,\n return 0;\n }\n \n-static int fetch_guest_state(CPUState *cpu)\n-{\n- int ret;\n-\n- ret = mshv_get_standard_regs(cpu);\n- if (ret < 0) {\n- error_report(\"Failed to get standard registers\");\n- return -1;\n- }\n-\n- ret = mshv_get_special_regs(cpu);\n- if (ret < 0) {\n- error_report(\"Failed to get special registers\");\n- return -1;\n- }\n-\n- return 0;\n-}\n-\n static int read_memory(const CPUState *cpu, uint64_t initial_gva,\n uint64_t initial_gpa, uint64_t gva, uint8_t *data,\n size_t len)\n@@ -1429,9 +1417,9 @@ static int handle_pio_str(CPUState *cpu, hv_x64_io_port_intercept_message *info)\n X86CPU *x86_cpu = X86_CPU(cpu);\n CPUX86State *env = &x86_cpu->env;\n \n- ret = fetch_guest_state(cpu);\n+ ret = mshv_arch_load_regs(cpu);\n if (ret < 0) {\n- error_report(\"Failed to fetch guest state\");\n+ error_report(\"Failed to load registers\");\n return -1;\n }\n \n@@ -1462,7 +1450,7 @@ static int handle_pio_str(CPUState *cpu, hv_x64_io_port_intercept_message *info)\n \n ret = set_x64_registers(cpu, reg_names, reg_values);\n if (ret < 0) {\n- error_report(\"Failed to set x64 registers\");\n+ error_report(\"Failed to set RIP and RAX registers\");\n return -1;\n }\n \n","prefixes":["01/34"]}