{"id":2224253,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2224253/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-tegra/patch/20260417073452.23342-2-clamor95@gmail.com/","project":{"id":21,"url":"http://patchwork.ozlabs.org/api/1.2/projects/21/?format=json","name":"Linux Tegra Development","link_name":"linux-tegra","list_id":"linux-tegra.vger.kernel.org","list_email":"linux-tegra@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260417073452.23342-2-clamor95@gmail.com>","list_archive_url":null,"date":"2026-04-17T07:34:52","name":"[v1,1/1] clk: tegra: support 48MHz clock for pll_p_out1","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"a89656f9da28ceb9be56db4fa9af251cdf808d8d","submitter":{"id":84146,"url":"http://patchwork.ozlabs.org/api/1.2/people/84146/?format=json","name":"Svyatoslav Ryhel","email":"clamor95@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-tegra/patch/20260417073452.23342-2-clamor95@gmail.com/mbox/","series":[{"id":500256,"url":"http://patchwork.ozlabs.org/api/1.2/series/500256/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-tegra/list/?series=500256","date":"2026-04-17T07:34:52","name":"clk: tegra: support 48MHz clock for pll_p_out1","version":1,"mbox":"http://patchwork.ozlabs.org/series/500256/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2224253/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2224253/checks/","tags":{},"related":[],"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-tegra@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=X9EEjVpq;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; 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charset=UTF-8","Content-Transfer-Encoding":"8bit"},"content":"From: Dmitry Osipenko \n\nUEFI on Surface2 sets pll_p_out1 to 48MHz which is not supported\nby kernel and causes BUG() early on. Fix this by adding 48MHz\nclock support for pll_p_out1 along with 48MHz support for pll_a,\nmain pll_p_out1 descendant.\n\nSigned-off-by: Dmitry Osipenko \nSigned-off-by: Jonas Schwöbel \nSigned-off-by: Svyatoslav Ryhel \n---\n drivers/clk/tegra/clk-pll.c | 1 +\n drivers/clk/tegra/clk-tegra114.c | 6 ++++--\n 2 files changed, 5 insertions(+), 2 deletions(-)","diff":"diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c\nindex d86003b6d94f..eae732320bec 100644\n--- a/drivers/clk/tegra/clk-pll.c\n+++ b/drivers/clk/tegra/clk-pll.c\n@@ -564,6 +564,7 @@ static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,\n \tswitch (parent_rate) {\n \tcase 12000000:\n \tcase 26000000:\n+\tcase 48000000:\n \t\tcfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000;\n \t\tbreak;\n \tcase 13000000:\ndiff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c\nindex a4f40533cc43..6a77742aaad2 100644\n--- a/drivers/clk/tegra/clk-tegra114.c\n+++ b/drivers/clk/tegra/clk-tegra114.c\n@@ -363,13 +363,15 @@ static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {\n \t{ 28800000, 282240000, 245, 25, 1, 8 },\n \t{ 28800000, 368640000, 320, 25, 1, 8 },\n \t{ 28800000, 240000000, 200, 24, 1, 8 },\n+\t{ 48000000, 282240000, 147, 25, 1, 8 },\n+\t{ 48000000, 368640000, 192, 25, 1, 8 },\n+\t{ 48000000, 564480000, 294, 25, 1, 8 },\n \t{ 0, 0, 0, 0, 0, 0 },\n };\n \n-\n static struct tegra_clk_pll_params pll_a_params = {\n \t.input_min = 2000000,\n-\t.input_max = 31000000,\n+\t.input_max = 48000000,\n \t.cf_min = 1000000,\n \t.cf_max = 6000000,\n \t.vco_min = 200000000,\n","prefixes":["v1","1/1"]}