{"id":2224218,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2224218/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260416-setmaxopp-v1-1-6a74e2d945a0@oss.qualcomm.com/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/1.2/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260416-setmaxopp-v1-1-6a74e2d945a0@oss.qualcomm.com>","list_archive_url":null,"date":"2026-04-17T04:16:25","name":"PCI: qcom: Set max OPP before DBI access during resume","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"29a99785e138e5c0cb98a02aec4d68f395a8b6b2","submitter":{"id":90999,"url":"http://patchwork.ozlabs.org/api/1.2/people/90999/?format=json","name":"Qiang Yu","email":"qiang.yu@oss.qualcomm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260416-setmaxopp-v1-1-6a74e2d945a0@oss.qualcomm.com/mbox/","series":[{"id":500236,"url":"http://patchwork.ozlabs.org/api/1.2/series/500236/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/list/?series=500236","date":"2026-04-17T04:16:25","name":"PCI: qcom: Set max OPP before DBI access during resume","version":1,"mbox":"http://patchwork.ozlabs.org/series/500236/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2224218/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2224218/checks/","tags":{},"related":[],"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=NJzkkslN;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=Mhp5ZKlP;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; 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a=ed25519;\n pk=Rr94t+fykoieF1ngg/bXxEfr5KoQxeXPtYxM8fBQTAI=","X-Proofpoint-GUID":"Rcv9RNs-a3q5D_RD--3pXmvJsTXZcqP2","X-Authority-Analysis":"v=2.4 cv=XNoAjwhE c=1 sm=1 tr=0 ts=69e1b41d cx=c_pps\n a=Uww141gWH0fZj/3QKPojxA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17\n a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10\n a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22\n a=EUspDBNiAAAA:8 a=_e_GtX_bwWpn_Ay3u5MA:9 a=QEXdDO2ut3YA:10\n a=PxkB5W3o20Ba91AHUih5:22","X-Proofpoint-ORIG-GUID":"Rcv9RNs-a3q5D_RD--3pXmvJsTXZcqP2","X-Proofpoint-Spam-Details-Enc":"AW1haW4tMjYwNDE3MDAzOSBTYWx0ZWRfX7p7I84NGcth3\n zRw1xKhUiH5rgd50X+D4rkcjM80VRZ45THljTo2vLjKxjmetlfpAZO3CtYp5JWE3S/CuCkZsAg0\n /eZErFipa1ySTVbISIAMTnUxj/ua0wh0dq9pMvyKnAei2QS9rDMxfBW5aKqy1qGNz+W2yIIQ6vG\n IEU0pjpRrkxsCG3USEHV9T+x/XotTnPTXDi9RhbwYd4B7vd7BtKtXS2aPzW950y2qJb6WigUtaa\n 5W1xVgY4v5bNfSre2JzfbU8rtiP9bimaZIAQwkBFjcz1pxW7LKIlJCAUBdLdyiLEkN8k5NZv1OL\n 3eba0dWzyQuiy1gijxdeXW9HLioVPIps4BsCqSTdnLe0fLZ0H958POmaNn908awHE6fPZalJAVg\n d1uZj/qnK64n808bOptYEbmfL/Vvb9eAJ5q/x/to6aE33SSswxoEB7iUL7lJZP6Ygr7Cv4scUyU\n EFo33Oo/eV+MXROR1ig==","X-Proofpoint-Virus-Version":"vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-16_04,2026-04-16_03,2025-10-01_01","X-Proofpoint-Spam-Details":"rule=outbound_notspam policy=outbound score=0\n malwarescore=0 impostorscore=0 priorityscore=1501 suspectscore=0 spamscore=0\n phishscore=0 clxscore=1011 lowpriorityscore=0 adultscore=0 bulkscore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2604070000 definitions=main-2604170039"},"content":"During resume, qcom_pcie_icc_opp_update() may access DBI registers before\nthe OPP votes are restored, which can trigger NoC errors.\n\nSet the PCIe controller to the maximum OPP first in resume_noirq(), then\nproceed with link/DBI accesses. The OPP is later updated again based on\nthe actual link bandwidth requirements.\n\nAlso introduce a small helper to reuse the max-OPP setup path shared with\nprobe.\n\nFixes: 5b6272e0efd5 (\"PCI: qcom: Add OPP support to scale performance\")\nSigned-off-by: Qiang Yu \n---\n drivers/pci/controller/dwc/pcie-qcom.c | 42 +++++++++++++++++++++-------------\n 1 file changed, 26 insertions(+), 16 deletions(-)\n\n\n---\nbase-commit: 33a76fc3c3e61386524479b99f35423bd3d9a895\nchange-id: 20260416-setmaxopp-7a4f49fb90b5\n\nBest regards,","diff":"diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c\nindex 9fdfc88ac15120b2b01cad746772ae612a2c9690..c9b201a1c033a9849e97db9ee4d07d26655d5a6c 100644\n--- a/drivers/pci/controller/dwc/pcie-qcom.c\n+++ b/drivers/pci/controller/dwc/pcie-qcom.c\n@@ -1613,6 +1613,22 @@ static void qcom_pcie_icc_opp_update(struct qcom_pcie *pcie)\n \t}\n }\n \n+static int qcom_pcie_set_max_opp(struct device *dev)\n+{\n+\tunsigned long max_freq = ULONG_MAX;\n+\tstruct dev_pm_opp *opp;\n+\tint ret;\n+\n+\topp = dev_pm_opp_find_freq_floor(dev, &max_freq);\n+\tif (IS_ERR(opp))\n+\t\treturn PTR_ERR(opp);\n+\n+\tret = dev_pm_opp_set_opp(dev, opp);\n+\tdev_pm_opp_put(opp);\n+\n+\treturn ret;\n+}\n+\n static int qcom_pcie_link_transition_count(struct seq_file *s, void *data)\n {\n \tstruct qcom_pcie *pcie = (struct qcom_pcie *)dev_get_drvdata(s->private);\n@@ -1845,9 +1861,7 @@ static int qcom_pcie_probe(struct platform_device *pdev)\n \tstruct qcom_pcie_perst *perst, *tmp_perst;\n \tstruct qcom_pcie_port *port, *tmp_port;\n \tconst struct qcom_pcie_cfg *pcie_cfg;\n-\tunsigned long max_freq = ULONG_MAX;\n \tstruct device *dev = &pdev->dev;\n-\tstruct dev_pm_opp *opp;\n \tstruct qcom_pcie *pcie;\n \tstruct dw_pcie_rp *pp;\n \tstruct resource *res;\n@@ -1951,21 +1965,9 @@ static int qcom_pcie_probe(struct platform_device *pdev)\n \t * probe(), OPP will be updated using qcom_pcie_icc_opp_update().\n \t */\n \tif (!ret) {\n-\t\topp = dev_pm_opp_find_freq_floor(dev, &max_freq);\n-\t\tif (IS_ERR(opp)) {\n-\t\t\tret = PTR_ERR(opp);\n-\t\t\tdev_err_probe(pci->dev, ret,\n-\t\t\t\t \"Unable to find max freq OPP\\n\");\n-\t\t\tgoto err_pm_runtime_put;\n-\t\t} else {\n-\t\t\tret = dev_pm_opp_set_opp(dev, opp);\n-\t\t}\n-\n-\t\tdev_pm_opp_put(opp);\n+\t\tret = qcom_pcie_set_max_opp(dev);\n \t\tif (ret) {\n-\t\t\tdev_err_probe(pci->dev, ret,\n-\t\t\t\t \"Failed to set OPP for freq %lu\\n\",\n-\t\t\t\t max_freq);\n+\t\t\tdev_err_probe(dev, ret, \"Failed to set max OPP in probe\\n\");\n \t\t\tgoto err_pm_runtime_put;\n \t\t}\n \n@@ -2100,6 +2102,14 @@ static int qcom_pcie_resume_noirq(struct device *dev)\n \t\treturn 0;\n \n \tif (pm_suspend_target_state != PM_SUSPEND_MEM) {\n+\t\tif (pcie->use_pm_opp) {\n+\t\t\tret = qcom_pcie_set_max_opp(dev);\n+\t\t\tif (ret) {\n+\t\t\t\tdev_err(dev, \"Failed to set max OPP in resume: %d\\n\", ret);\n+\t\t\t\treturn ret;\n+\t\t\t}\n+\t\t}\n+\n \t\tret = icc_enable(pcie->icc_cpu);\n \t\tif (ret) {\n \t\t\tdev_err(dev, \"Failed to enable CPU-PCIe interconnect path: %d\\n\", ret);\n","prefixes":[]}