{"id":2224212,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2224212/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417035734.32334-5-philmd@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260417035734.32334-5-philmd@linaro.org>","list_archive_url":null,"date":"2026-04-17T03:57:34","name":"[v5,4/4] target/mips: Check alignment for microMIPS pre-R6 LD/ST multiple","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"80270236614d7501e5604c2ec757125183772962","submitter":{"id":85046,"url":"http://patchwork.ozlabs.org/api/1.2/people/85046/?format=json","name":"Philippe Mathieu-Daudé","email":"philmd@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417035734.32334-5-philmd@linaro.org/mbox/","series":[{"id":500232,"url":"http://patchwork.ozlabs.org/api/1.2/series/500232/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500232","date":"2026-04-17T03:57:30","name":"target/mips: Replace cpu_ld/st_mmuidx_ra() calls in LD/ST Multiple","version":5,"mbox":"http://patchwork.ozlabs.org/series/500232/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2224212/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2224212/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=rJ1/gILG;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2a00:1450:4864:20::333;\n envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Pre-REL6 microMIPS requires alignment while REL6 microMIPS does not.\nUse @default_tcg_memop_mask in gen_ldst_multiple(), it is set to\nMO_UNALN for REL6 but MO_ALIGN for pre-REL6.\n\nFixes: 3c824109da0 (\"target-mips: microMIPS ASE support\")\nReported-by: Richard Henderson \nSigned-off-by: Philippe Mathieu-Daudé \n---\nGood enough until making it explicit in a decodetree conversion.\n---\n target/mips/tcg/micromips_translate.c.inc | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)","diff":"diff --git a/target/mips/tcg/micromips_translate.c.inc b/target/mips/tcg/micromips_translate.c.inc\nindex fb107eb91fe..da2419792eb 100644\n--- a/target/mips/tcg/micromips_translate.c.inc\n+++ b/target/mips/tcg/micromips_translate.c.inc\n@@ -693,7 +693,7 @@ static void gen_ldst_multiple(DisasContext *ctx, uint32_t opc, int reglist,\n int base, int16_t offset)\n {\n TCGv t0, t1;\n- MemOp mop = MO_UNALN;\n+ MemOp mop = ctx->default_tcg_memop_mask;\n MemOpIdx oi;\n \n if (ctx->hflags & MIPS_HFLAG_BMASK) {\n","prefixes":["v5","4/4"]}