{"id":2223506,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2223506/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/20260415120425.5792-6-sgdfkk@163.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/1.2/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260415120425.5792-6-sgdfkk@163.com>","list_archive_url":null,"date":"2026-04-15T12:04:11","name":"[v7,5/7] mips: loongson: add clk driver","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"f45b7c80f7143e04d232b9fe3b330540a6ff042d","submitter":{"id":92844,"url":"http://patchwork.ozlabs.org/api/1.2/people/92844/?format=json","name":null,"email":"sgdfkk@163.com"},"delegate":{"id":4307,"url":"http://patchwork.ozlabs.org/api/1.2/users/4307/?format=json","username":"danielschwierzeck","first_name":"Daniel","last_name":"Schwierzeck","email":"daniel.schwierzeck@googlemail.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/20260415120425.5792-6-sgdfkk@163.com/mbox/","series":[{"id":499983,"url":"http://patchwork.ozlabs.org/api/1.2/series/499983/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=499983","date":"2026-04-15T12:04:09","name":null,"version":7,"mbox":"http://patchwork.ozlabs.org/series/499983/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2223506/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2223506/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=163.com header.i=@163.com header.a=rsa-sha256\n header.s=s110527 header.b=WDysM2OO;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)","phobos.denx.de;\n dmarc=pass (p=none dis=none) header.from=163.com","phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de","phobos.denx.de;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=163.com header.i=@163.com header.b=\"WDysM2OO\";\n\tdkim-atps=neutral","phobos.denx.de;\n dmarc=pass (p=none dis=none) header.from=163.com","phobos.denx.de; spf=pass smtp.mailfrom=sgdfkk@163.com"],"Received":["from phobos.denx.de (phobos.denx.de\n [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fwfx05g8Jz1yCv\n\tfor ; Wed, 15 Apr 2026 22:05:40 +1000 (AEST)","from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id 7DBFC84207;\n\tWed, 15 Apr 2026 14:05:25 +0200 (CEST)","by phobos.denx.de (Postfix, from userid 109)\n id 1065483936; Wed, 15 Apr 2026 14:05:18 +0200 (CEST)","from m16.mail.163.com (m16.mail.163.com [117.135.210.3])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 811B583936\n for ; Wed, 15 Apr 2026 14:05:15 +0200 (CEST)","from server-e.. (unknown [])\n by gzga-smtp-mtada-g1-0 (Coremail) with SMTP id\n _____wD3RcLJft9p2XkzFA--.19463S7;\n Wed, 15 Apr 2026 20:04:47 +0800 (CST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-0.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,\n DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,HK_RANDOM_ENVFROM,\n HK_RANDOM_FROM,RCVD_IN_DNSWL_BLOCKED,RCVD_IN_MSPIKE_H2,\n RCVD_IN_VALIDITY_CERTIFIED_BLOCKED,RCVD_IN_VALIDITY_RPBL_BLOCKED,\n SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY autolearn=no\n autolearn_force=no version=3.4.2","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com;\n s=s110527; h=From:To:Subject:Date:Message-ID:MIME-Version; bh=Y8\n 4239WcusOVETQkP2aaviIZ6D2nXxGGjtUZkDjPhdY=; b=WDysM2OOjRL5y4YbtX\n 8pAhPE6BXqin5gx9VKOoZC3vqrgpn0cJ4JGKDR1ZoAGegap/747cfOB3WFNzk7R9\n gg7VPDV/qHm2jGhDDxXh6jZxdUf0nWtqpTo9TjyU6naTPu15wgURHQsbxXX7E8V2\n CtDfNcVgfh/ZxjL5vThb4Ssls=","From":"sgdfkk@163.com","To":"duhuanpeng@139.com","Cc":"Du Huanpeng , Tom Rini ,\n Lukasz Majewski , Leo Yu-Chi Liang ,\n Yao Zi , u-boot@lists.denx.de (open list)","Subject":"[PATCH v7 5/7] mips: loongson: add clk driver","Date":"Wed, 15 Apr 2026 20:04:11 +0800","Message-ID":"<20260415120425.5792-6-sgdfkk@163.com>","X-Mailer":"git-send-email 2.43.0","In-Reply-To":"<20260415120425.5792-1-sgdfkk@163.com>","References":"<20260415120425.5792-1-sgdfkk@163.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-CM-TRANSID":"_____wD3RcLJft9p2XkzFA--.19463S7","X-Coremail-Antispam":"1Uf129KBjvJXoWxKF4DJry7XF4DWr15Ar45trb_yoW7KF4xpa\n nYkFWrKr4Yq3y7G3WfJFyUJFySkF10yFyUurZFga4SkFnxAF4jqFs2ga43tF45CF97X3yY\n q3WqgrWxCFZFvaUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2\n 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x07j7qXQUUUUU=","X-Originating-IP":"[240e:3b0:4805:31e::3001]","X-CM-SenderInfo":"xvjgwyrn6rljoofrz/xtbCwB8pgGnfft97iwAA3R","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.39","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" ","X-Virus-Scanned":"clamav-milter 0.103.8 at phobos.denx.de","X-Virus-Status":"Clean"},"content":"From: Du Huanpeng \n\nclk driver loongson mips for embedded SoC ls1c300\n\nSigned-off-by: Du Huanpeng \n---\n drivers/clk/Makefile | 1 +\n drivers/clk/loongson/Makefile | 3 +\n drivers/clk/loongson/clk-ls1c300.c | 186 +++++++++++++++++++++++++++++\n 3 files changed, 190 insertions(+)\n create mode 100644 drivers/clk/loongson/Makefile\n create mode 100644 drivers/clk/loongson/clk-ls1c300.c","diff":"diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile\nindex 5f0c0d8a5c2..e19bb17276e 100644\n--- a/drivers/clk/Makefile\n+++ b/drivers/clk/Makefile\n@@ -23,6 +23,7 @@ obj-y += ti/\n obj-$(CONFIG_CLK_THEAD) += thead/\n obj-$(CONFIG_$(PHASE_)CLK_INTEL) += intel/\n obj-$(CONFIG_ARCH_ASPEED) += aspeed/\n+obj-$(CONFIG_ARCH_LSMIPS) += loongson/\n obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/\n obj-$(CONFIG_ARCH_MESON) += meson/\n obj-$(CONFIG_ARCH_MTMIPS) += mtmips/\ndiff --git a/drivers/clk/loongson/Makefile b/drivers/clk/loongson/Makefile\nnew file mode 100644\nindex 00000000000..0a47269cd30\n--- /dev/null\n+++ b/drivers/clk/loongson/Makefile\n@@ -0,0 +1,3 @@\n+# SPDX-License-Identifier: GPL-2.0\n+\n+obj-$(CONFIG_SOC_LS1C300) += clk-ls1c300.o\ndiff --git a/drivers/clk/loongson/clk-ls1c300.c b/drivers/clk/loongson/clk-ls1c300.c\nnew file mode 100644\nindex 00000000000..0aa7470fe28\n--- /dev/null\n+++ b/drivers/clk/loongson/clk-ls1c300.c\n@@ -0,0 +1,186 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * reference:\n+ * drivers/clk/microchip/mpfs_clk.c\n+ * drivers/clk/clk_octeon.c\n+ *\n+ * Copyright (C) 2020-2026 Du Huanpeng \n+ */\n+\n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+\n+/* PLL/SDRAM Frequency Configuration Register */\n+#define START_FREQ\t0\n+#define CLK_DIV_PARAM\t4\n+\n+/* START_FREQ */\n+#define\tPLL_VALID\tBIT(31)\n+#define\tRESERVED0\tGENMASK(30, 24)\n+#define\tFRAC_N\t\tGENMASK(23, 16)\n+#define\tM_PLL\t\tGENMASK(15, 8)\n+#define\tRESERVED1\tGENMASK(7, 4)\n+#define\tRST_TIME\tGENMASK(3, 2)\n+#define\tSDRAM_DIV\tGENMASK(1, 0)\n+/* CLK_DIV_PARAM */\n+#define\tPIX_DIV\t\tGENMASK(31, 24)\n+#define\tCAM_DIV\t\tGENMASK(23, 16)\n+#define\tCPU_DIV\t\tGENMASK(15, 8)\n+#define\tRESERVED2\tGENMASK(7, 6)\n+#define\tPIX_DIV_VALID\tBIT(5)\n+#define\tPIX_SEL\t\tBIT(4)\n+#define\tCAM_DIV_VALID\tBIT(3)\n+#define\tCAM_SEL\t\tBIT(2)\n+#define\tCPU_DIV_VALID\tBIT(1)\n+#define\tCPU_SEL\t\tBIT(0)\n+/* CPU_THROT */\n+#define\tCPU_THROT\tGENMASK(3, 0)\n+\n+struct ls1c300_clk_priv {\n+\tstruct clk pll;\n+\tstruct clk throt;\n+};\n+\n+static const struct clk_div_table sdram_div_table[] = {\n+\t{.val = 0, .div = 2},\n+\t{.val = 1, .div = 4},\n+\t{.val = 2, .div = 3},\n+\t{.val = 3, .div = 3},\n+};\n+\n+ulong ls1c300_pll_get_rate(struct clk *clk)\n+{\n+\tunsigned int mult;\n+\tlong long parent_rate;\n+\tvoid *base;\n+\tunsigned int val;\n+\n+\tparent_rate = clk_get_parent_rate(clk);\n+\tbase = (void *)clk->data;\n+\n+\tval = readl(base + START_FREQ);\n+\tmult = FIELD_GET(FRAC_N, val) + FIELD_GET(M_PLL, val);\n+\treturn (mult * parent_rate) / 4;\n+}\n+\n+static ulong ls1c300_clk_get_rate(struct clk *clk)\n+{\n+\tstruct clk *cl;\n+\tulong rate;\n+\tint err;\n+\n+\terr = clk_get_by_id(clk->id, &cl);\n+\tif (err)\n+\t\treturn err;\n+\n+\trate = clk_get_rate(cl);\n+\treturn rate;\n+}\n+\n+static int ls1c300_clk_probe(struct udevice *dev)\n+{\n+\tvoid __iomem *base;\n+\tvoid __iomem *cpu_throt;\n+\tvoid __iomem *addr;\n+\n+\tstruct ls1c300_clk_priv *priv;\n+\n+\tstruct clk *cl, clk;\n+\tconst char *parent_name;\n+\tint flags;\n+\tint ret;\n+\n+\tbase = dev_remap_addr_index(dev, 0);\n+\tcpu_throt = dev_remap_addr_index(dev, 1);\n+\n+\tret = clk_get_by_index(dev, 0, &clk);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = clk_get_rate(&clk);\n+\tparent_name = clk.dev->name;\n+\n+\tpriv = dev_get_priv(dev);\n+\tcl = &priv->pll;\n+\tcl->data = (unsigned long)base;\n+\tret = clk_register(cl, \"clk_ls1c300_pll\", \"pll\", parent_name);\n+\tclk_dm(CLK_PLL, cl);\n+\n+\taddr = base + CLK_DIV_PARAM;\n+\tflags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO;\n+\tcl = clk_register_divider(NULL, \"cpu_div\", \"pll\", 0, addr, 8, 7, flags);\n+\tclk_dm(CLK_CPU, cl);\n+\tcl = clk_register_divider(NULL, \"cam_div\", \"pll\", 0, addr, 16, 7, flags);\n+\tclk_dm(CLK_CAMERA, cl);\n+\tcl = clk_register_divider(NULL, \"pix_div\", \"pll\", 0, addr, 24, 7, flags);\n+\tclk_dm(CLK_PIX, cl);\n+\n+\tcl = &priv->throt;\n+\tcl->data = (unsigned long)cpu_throt;\n+\tret = clk_register(cl, \"clk_cpu_throt\", \"cpu_throt_factor\", \"cpu_div\");\n+\tclk_dm(CLK_CPU_THROT, cl);\n+\n+\taddr = base + START_FREQ;\n+\tcl = clk_register_divider(NULL, \"sdram_div\", \"cpu_div\", 0, addr, 0, 2, 0);\n+\tto_clk_divider(cl)->table = sdram_div_table;\n+\tclk_dm(CLK_APB, cl);\n+\n+\treturn 0;\n+}\n+\n+static ulong cpu_throt_get_rate(struct clk *clk)\n+{\n+\tvoid __iomem *cpu_throt;\n+\tlong long parent_rate;\n+\tulong ret;\n+\n+\tparent_rate = clk_get_parent_rate(clk);\n+\tcpu_throt = (void *)clk->data;\n+\n+\tret = readl(cpu_throt) + 1;\n+\tret = parent_rate * ret / 16;\n+\treturn ret;\n+}\n+\n+static const struct udevice_id ls1c300_clk_ids[] = {\n+\t{ .compatible = \"loongson,ls1c300-clk\" },\n+\t{ }\n+};\n+\n+static const struct clk_ops clk_cpu_throt_ops = {\n+\t.get_rate = cpu_throt_get_rate,\n+};\n+\n+static const struct clk_ops clk_ls1c300_pll_ops = {\n+\t.get_rate = ls1c300_pll_get_rate,\n+};\n+\n+static const struct clk_ops ls1c300_clk_ops = {\n+\t.get_rate = ls1c300_clk_get_rate,\n+};\n+\n+U_BOOT_DRIVER(clk_ls1c300_cpu_throt) = {\n+\t.name\t= \"clk_cpu_throt\",\n+\t.id\t= UCLASS_CLK,\n+\t.ops\t= &clk_cpu_throt_ops,\n+};\n+\n+U_BOOT_DRIVER(clk_ls1c300_pll) = {\n+\t.name\t= \"clk_ls1c300_pll\",\n+\t.id\t= UCLASS_CLK,\n+\t.ops\t= &clk_ls1c300_pll_ops,\n+};\n+\n+U_BOOT_DRIVER(ls1c300_clk) = {\n+\t.name = \"clk_ls1c300\",\n+\t.id = UCLASS_CLK,\n+\t.of_match = ls1c300_clk_ids,\n+\t.probe = ls1c300_clk_probe,\n+\t.priv_auto = sizeof(struct ls1c300_clk_priv),\n+\t.ops = &ls1c300_clk_ops,\n+};\n","prefixes":["v7","5/7"]}