{"id":2223491,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2223491/?format=json","web_url":"http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20260415112706.1562382-2-przemyslaw.korba@intel.com/","project":{"id":46,"url":"http://patchwork.ozlabs.org/api/1.2/projects/46/?format=json","name":"Intel Wired Ethernet development","link_name":"intel-wired-lan","list_id":"intel-wired-lan.osuosl.org","list_email":"intel-wired-lan@osuosl.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260415112706.1562382-2-przemyslaw.korba@intel.com>","list_archive_url":null,"date":"2026-04-15T11:27:05","name":"[iwl-next] ice: add SBQ posted writes with non-posted support for CGU","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"00d2f61cebf9aea74ad420fcd2df2257aabdb49c","submitter":{"id":89670,"url":"http://patchwork.ozlabs.org/api/1.2/people/89670/?format=json","name":"Przemyslaw Korba","email":"przemyslaw.korba@intel.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20260415112706.1562382-2-przemyslaw.korba@intel.com/mbox/","series":[{"id":499976,"url":"http://patchwork.ozlabs.org/api/1.2/series/499976/?format=json","web_url":"http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=499976","date":"2026-04-15T11:27:05","name":"[iwl-next] ice: add SBQ posted writes with non-posted support for CGU","version":1,"mbox":"http://patchwork.ozlabs.org/series/499976/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2223491/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2223491/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","intel-wired-lan@lists.osuosl.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","intel-wired-lan@lists.osuosl.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=osuosl.org header.i=@osuosl.org header.a=rsa-sha256\n header.s=default header.b=B4CiqFiv;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=osuosl.org\n (client-ip=2605:bc80:3010::137; helo=smtp4.osuosl.org;\n envelope-from=intel-wired-lan-bounces@osuosl.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from smtp4.osuosl.org (smtp4.osuosl.org [IPv6:2605:bc80:3010::137])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fwf3d174Lz1yHM\n\tfor ; Wed, 15 Apr 2026 21:26:21 +1000 (AEST)","from localhost (localhost [127.0.0.1])\n\tby smtp4.osuosl.org (Postfix) with ESMTP id 77E0B47995;\n\tWed, 15 Apr 2026 11:26:19 +0000 (UTC)","from smtp4.osuosl.org ([127.0.0.1])\n by localhost (smtp4.osuosl.org [127.0.0.1]) (amavis, port 10024) with ESMTP\n id sci9un_ePba8; Wed, 15 Apr 2026 11:26:18 +0000 (UTC)","from lists1.osuosl.org (lists1.osuosl.org [140.211.166.142])\n\tby smtp4.osuosl.org (Postfix) with ESMTP id A863847135;\n\tWed, 15 Apr 2026 11:26:18 +0000 (UTC)","from smtp1.osuosl.org (smtp1.osuosl.org [IPv6:2605:bc80:3010::138])\n by lists1.osuosl.org (Postfix) with ESMTP id DE5B2283\n for ; Wed, 15 Apr 2026 11:26:17 +0000 (UTC)","from localhost (localhost [127.0.0.1])\n by smtp1.osuosl.org (Postfix) with ESMTP id D03BD853BD\n for ; Wed, 15 Apr 2026 11:26:17 +0000 (UTC)","from smtp1.osuosl.org ([127.0.0.1])\n by localhost (smtp1.osuosl.org [127.0.0.1]) (amavis, port 10024) with ESMTP\n id PCDtpnPiY-FP for ;\n Wed, 15 Apr 2026 11:26:17 +0000 (UTC)","from mgamail.intel.com (mgamail.intel.com [198.175.65.10])\n by smtp1.osuosl.org (Postfix) with ESMTPS id 06D8D82ED2\n for ; Wed, 15 Apr 2026 11:26:16 +0000 (UTC)","from fmviesa003.fm.intel.com ([10.60.135.143])\n by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 15 Apr 2026 04:26:17 -0700","from pae-d-dell-r7525-263.igk.intel.com ([172.28.191.240])\n by fmviesa003.fm.intel.com with ESMTP; 15 Apr 2026 04:26:14 -0700"],"X-Virus-Scanned":["amavis at osuosl.org","amavis at osuosl.org"],"X-Comment":"SPF check N/A for local connections - client-ip=140.211.166.142;\n helo=lists1.osuosl.org; envelope-from=intel-wired-lan-bounces@osuosl.org;\n receiver= ","DKIM-Filter":["OpenDKIM Filter v2.11.0 smtp4.osuosl.org A863847135","OpenDKIM Filter v2.11.0 smtp1.osuosl.org 06D8D82ED2"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=osuosl.org;\n\ts=default; t=1776252378;\n\tbh=iZpVUgANLHe9bJT14MDPaLHB9doID5pO17wzLlwEfVY=;\n\th=From:To:Cc:Date:Subject:List-Id:List-Unsubscribe:List-Archive:\n\t List-Post:List-Help:List-Subscribe:From;\n\tb=B4CiqFivbceyN5mcfI2M59ac+R32Zt5fnmpP9uRrZ4rF4wk5hcRQQbmwSfEB8umWW\n\t c3yYWcSCxGzeJqGVyxsA1jNwFilkJUVMw3DkaaPaEg0kEu6bngvlX9MLgB8wTgnA7h\n\t TdfgFBZARuiU/5ofLX1HeeC64DT39lY40MnoEldJCW+Tpwrw3O/PPiDmMe7OQc1c8v\n\t X19FnzlMG3CUE8KP0/3t2npawZ3wJqvGajMh9Mput1AikV7FCmYqToDzrK5T2+CQTc\n\t pbvOZ6MgBWz+UMNAU+r7Bg9POMxPHMhjzhjH5j0n/XlPRsxF1KfMgN9yLxtq2459Ez\n\t fLOsXFnu8eEhw==","Received-SPF":"Pass (mailfrom) identity=mailfrom; client-ip=198.175.65.10;\n helo=mgamail.intel.com; envelope-from=przemyslaw.korba@intel.com;\n receiver=","DMARC-Filter":"OpenDMARC Filter v1.4.2 smtp1.osuosl.org 06D8D82ED2","X-CSE-ConnectionGUID":["w+0FPs07R4GrBDmKEnq1zw==","cFiMoeY0QKWnbnpjPLr5Fg=="],"X-CSE-MsgGUID":["ZlLbcro1SbWDm369tbGApA==","5o0dAeXFQk+/x73ulD9N8Q=="],"X-IronPort-AV":["E=McAfee;i=\"6800,10657,11759\"; a=\"94626762\"","E=Sophos;i=\"6.23,179,1770624000\"; d=\"scan'208\";a=\"94626762\""],"X-ExtLoop1":"1","From":"Przemyslaw Korba ","To":"intel-wired-lan@lists.osuosl.org","Cc":"netdev@vger.kernel.org, anthony.l.nguyen@intel.com,\n przemyslaw.kitszel@intel.com,\n Przemyslaw Korba ,\n Aleksandr Loktionov ,\n Arkadiusz Kubalewski ","Date":"Wed, 15 Apr 2026 13:27:05 +0200","Message-ID":"<20260415112706.1562382-2-przemyslaw.korba@intel.com>","X-Mailer":"git-send-email 2.43.0","MIME-Version":"1.0","Content-Type":"text/plain; charset=UTF-8","Content-Transfer-Encoding":"8bit","X-Mailman-Original-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1776252377; x=1807788377;\n h=from:to:cc:subject:date:message-id:mime-version:\n content-transfer-encoding;\n bh=eIZb6zCxsJfPaW4k4tZ8a8BEq2ntgaMYL7LfKkdt5ho=;\n b=A9Lm+RmlzcVppj/xnWAiyYWLasOhAn0s5TOl8DwGuVh6PPspzns3dbTu\n oLmxTcSvDNcz04XQLxTAEtimaMA3+C1O59UXB5+Q8ZFPN1mjJmxFRl9Hv\n J6ZFDsqcOwZtoC9hF0c4XDrQl0V4TJPNHnrVegcFyY3cYqaUvy8K+5rW2\n H0etcE7PIOx0RHGaNls9Oy5FyDHIBHeQvfChd+VGwXkYDMiZZAKMYVXQu\n TCHB+tg7GcGdnWUMuIq0L5F9VxMXPM6O1xlCPddm5iNEIFPKXPMenFSNh\n w3guVcbcUoucJwWOEjbPP8w7jedAy6n9fYTwjZ6F77djm4f4uTo7MXm+M\n w==;","X-Mailman-Original-Authentication-Results":["smtp1.osuosl.org;\n dmarc=pass (p=none dis=none)\n header.from=intel.com","smtp1.osuosl.org;\n dkim=pass (2048-bit key,\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=A9Lm+Rml"],"Subject":"[Intel-wired-lan] [PATCH iwl-next] ice: add SBQ posted writes with\n non-posted support for CGU","X-BeenThere":"intel-wired-lan@osuosl.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Intel Wired Ethernet Linux Kernel Driver Development\n ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"intel-wired-lan-bounces@osuosl.org","Sender":"\"Intel-wired-lan\" "},"content":"From: Karol Kolacinski \n\nSideband queue (SBQ) is a HW queue with very short completion time. All\nSBQ writes were posted by default, which means that the driver did not\nhave to wait for completion from the neighbor device, because there was\nnone. This introduced unnecessary delays, where only those delays were\n\"ensuring\" that the command is \"completed\" and this was a potential race\ncondition.\n\nAdd the possibility to perform non-posted writes where it's necessary to\nwait for completion, instead of relying on fake completion from the FW,\nwhere only the delays are guarding the writes.\n\nFlush the SBQ by reading address 0 from the PHY 0 before issuing SYNC\ncommand to ensure that writes to all PHYs were completed and skip SBQ\nmessage completion if it's posted.\n\nTo analyze if delays are gone, look for and compare time spent in\nice_sq_send_cmd — posted writes should return immediately after the wr32.\nThat can be done for example by adjusting phc time with phc_ctl on E830\ndevice, for less than 2 seconds to use this new mechanism. Without it,\ncommand below will fail.\n\nReproduction steps:\nphc_ctl eth13 adj 1\nphc_ctl[4478170.994]: adjusted clock by 1.000000 seconds\n\nCheck trace for timing for comparisions:\necho ice_sbq_send_cmd > /sys/kernel/debug/tracing/set_ftrace_filter\necho function_graph > /sys/kernel/debug/tracing/current_tracer\ncat /sys/kernel/debug/tracing/trace\n\nTested on:\n - Intel E830 NIC (FW version 1.00)\n - Kernel 6.19.0+\n\nSigned-off-by: Karol Kolacinski \nSigned-off-by: Przemyslaw Korba \nReviewed-by: Aleksandr Loktionov \nReviewed-by: Arkadiusz Kubalewski \n---\n drivers/net/ethernet/intel/ice/ice_common.c | 18 ++++--\n drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 64 ++++++++++++--------\n drivers/net/ethernet/intel/ice/ice_sbq_cmd.h | 5 +-\n 3 files changed, 53 insertions(+), 34 deletions(-)\n\n\nbase-commit: 0851f49814a8899a9769619b50baaeef59f9ece4","diff":"diff --git a/drivers/net/ethernet/intel/ice/ice_common.c b/drivers/net/ethernet/intel/ice/ice_common.c\nindex f84990996530..2cd3d6d450a9 100644\n--- a/drivers/net/ethernet/intel/ice/ice_common.c\n+++ b/drivers/net/ethernet/intel/ice/ice_common.c\n@@ -1777,23 +1777,29 @@ int ice_sbq_rw_reg(struct ice_hw *hw, struct ice_sbq_msg_input *in, u16 flags)\n \tmsg.msg_addr_low = cpu_to_le16(in->msg_addr_low);\n \tmsg.msg_addr_high = cpu_to_le32(in->msg_addr_high);\n \n-\tif (in->opcode)\n+\tswitch (in->opcode) {\n+\tcase ice_sbq_msg_wr_p:\n+\tcase ice_sbq_msg_wr_np:\n \t\tmsg.data = cpu_to_le32(in->data);\n-\telse\n+\t\tbreak;\n+\tcase ice_sbq_msg_rd:\n \t\t/* data read comes back in completion, so shorten the struct by\n \t\t * sizeof(msg.data)\n \t\t */\n \t\tmsg_len -= sizeof(msg.data);\n+\t\tbreak;\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n \n-\tif (in->opcode == ice_sbq_msg_wr)\n-\t\tcd.posted = 1;\n+\tcd.posted = in->opcode == ice_sbq_msg_wr_p;\n \n \tdesc.flags = cpu_to_le16(flags);\n \tdesc.opcode = cpu_to_le16(ice_sbq_opc_neigh_dev_req);\n \tdesc.param0.cmd_len = cpu_to_le16(msg_len);\n \tstatus = ice_sbq_send_cmd(hw, &desc, &msg, msg_len, &cd);\n \n-\tif (!status && !in->opcode)\n+\tif (!status && in->opcode == ice_sbq_msg_rd)\n \t\tin->data = le32_to_cpu\n \t\t\t(((struct ice_sbq_msg_cmpl *)&msg)->data);\n \treturn status;\n@@ -6701,7 +6707,7 @@ int ice_write_cgu_reg(struct ice_hw *hw, u32 addr, u32 val)\n {\n \tstruct ice_sbq_msg_input cgu_msg = {\n \t\t.dest_dev = ice_get_dest_cgu(hw),\n-\t\t.opcode = ice_sbq_msg_wr,\n+\t\t.opcode = ice_sbq_msg_wr_np,\n \t\t.msg_addr_low = addr,\n \t\t.data = val\n \t};\ndiff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c\nindex 690f9d874443..0f202d4dae7c 100644\n--- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c\n+++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c\n@@ -368,6 +368,16 @@ void ice_ptp_src_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd)\n static void ice_ptp_exec_tmr_cmd(struct ice_hw *hw)\n {\n \tstruct ice_pf *pf = container_of(hw, struct ice_pf, hw);\n+\tstruct ice_sbq_msg_input msg = {\n+\t\t.dest_dev = ice_sbq_dev_phy_0,\n+\t\t.opcode = ice_sbq_msg_rd,\n+\t};\n+\tint err;\n+\n+\t/* Flush SBQ by reading address 0 on PHY 0 */\n+\terr = ice_sbq_rw_reg(hw, &msg, LIBIE_AQ_FLAG_RD);\n+\tif (err)\n+\t\tdev_warn(ice_hw_to_dev(hw), \"Failed to flush SBQ: %d\\n\", err);\n \n \tif (!ice_is_primary(hw))\n \t\thw = ice_get_primary_hw(pf);\n@@ -433,7 +443,7 @@ static int ice_write_phy_eth56g(struct ice_hw *hw, u8 port, u32 addr, u32 val)\n {\n \tstruct ice_sbq_msg_input msg = {\n \t\t.dest_dev = ice_ptp_get_dest_dev_e825(hw, port),\n-\t\t.opcode = ice_sbq_msg_wr,\n+\t\t.opcode = ice_sbq_msg_wr_p,\n \t\t.msg_addr_low = lower_16_bits(addr),\n \t\t.msg_addr_high = upper_16_bits(addr),\n \t\t.data = val\n@@ -2358,11 +2368,12 @@ static bool ice_is_40b_phy_reg_e82x(u16 low_addr, u16 *high_addr)\n static int\n ice_read_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 offset, u32 *val)\n {\n-\tstruct ice_sbq_msg_input msg = {0};\n+\tstruct ice_sbq_msg_input msg = {\n+\t\t.opcode = ice_sbq_msg_rd,\n+\t};\n \tint err;\n \n \tice_fill_phy_msg_e82x(hw, &msg, port, offset);\n-\tmsg.opcode = ice_sbq_msg_rd;\n \n \terr = ice_sbq_rw_reg(hw, &msg, LIBIE_AQ_FLAG_RD);\n \tif (err) {\n@@ -2435,12 +2446,13 @@ ice_read_64b_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 low_addr, u64 *val)\n static int\n ice_write_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 offset, u32 val)\n {\n-\tstruct ice_sbq_msg_input msg = {0};\n+\tstruct ice_sbq_msg_input msg = {\n+\t\t.opcode = ice_sbq_msg_wr_p,\n+\t\t.data = val\n+\t};\n \tint err;\n \n \tice_fill_phy_msg_e82x(hw, &msg, port, offset);\n-\tmsg.opcode = ice_sbq_msg_wr;\n-\tmsg.data = val;\n \n \terr = ice_sbq_rw_reg(hw, &msg, LIBIE_AQ_FLAG_RD);\n \tif (err) {\n@@ -2594,15 +2606,15 @@ static int ice_fill_quad_msg_e82x(struct ice_hw *hw,\n int\n ice_read_quad_reg_e82x(struct ice_hw *hw, u8 quad, u16 offset, u32 *val)\n {\n-\tstruct ice_sbq_msg_input msg = {0};\n+\tstruct ice_sbq_msg_input msg = {\n+\t\t.opcode = ice_sbq_msg_rd,\n+\t};\n \tint err;\n \n \terr = ice_fill_quad_msg_e82x(hw, &msg, quad, offset);\n \tif (err)\n \t\treturn err;\n \n-\tmsg.opcode = ice_sbq_msg_rd;\n-\n \terr = ice_sbq_rw_reg(hw, &msg, LIBIE_AQ_FLAG_RD);\n \tif (err) {\n \t\tice_debug(hw, ICE_DBG_PTP, \"Failed to send message to PHY, err %d\\n\",\n@@ -2628,16 +2640,16 @@ ice_read_quad_reg_e82x(struct ice_hw *hw, u8 quad, u16 offset, u32 *val)\n int\n ice_write_quad_reg_e82x(struct ice_hw *hw, u8 quad, u16 offset, u32 val)\n {\n-\tstruct ice_sbq_msg_input msg = {0};\n+\tstruct ice_sbq_msg_input msg = {\n+\t\t.opcode = ice_sbq_msg_wr_p,\n+\t\t.data = val\n+\t};\n \tint err;\n \n \terr = ice_fill_quad_msg_e82x(hw, &msg, quad, offset);\n \tif (err)\n \t\treturn err;\n \n-\tmsg.opcode = ice_sbq_msg_wr;\n-\tmsg.data = val;\n-\n \terr = ice_sbq_rw_reg(hw, &msg, LIBIE_AQ_FLAG_RD);\n \tif (err) {\n \t\tice_debug(hw, ICE_DBG_PTP, \"Failed to send message to PHY, err %d\\n\",\n@@ -4275,14 +4287,14 @@ static void ice_ptp_init_phy_e82x(struct ice_ptp_hw *ptp)\n */\n static int ice_read_phy_reg_e810(struct ice_hw *hw, u32 addr, u32 *val)\n {\n-\tstruct ice_sbq_msg_input msg = {0};\n+\tstruct ice_sbq_msg_input msg = {\n+\t\t.dest_dev = ice_sbq_dev_phy_0,\n+\t\t.opcode = ice_sbq_msg_rd,\n+\t\t.msg_addr_low = lower_16_bits(addr),\n+\t\t.msg_addr_high = upper_16_bits(addr),\n+\t};\n \tint err;\n \n-\tmsg.msg_addr_low = lower_16_bits(addr);\n-\tmsg.msg_addr_high = upper_16_bits(addr);\n-\tmsg.opcode = ice_sbq_msg_rd;\n-\tmsg.dest_dev = ice_sbq_dev_phy_0;\n-\n \terr = ice_sbq_rw_reg(hw, &msg, LIBIE_AQ_FLAG_RD);\n \tif (err) {\n \t\tice_debug(hw, ICE_DBG_PTP, \"Failed to send message to PHY, err %d\\n\",\n@@ -4305,15 +4317,15 @@ static int ice_read_phy_reg_e810(struct ice_hw *hw, u32 addr, u32 *val)\n */\n static int ice_write_phy_reg_e810(struct ice_hw *hw, u32 addr, u32 val)\n {\n-\tstruct ice_sbq_msg_input msg = {0};\n+\tstruct ice_sbq_msg_input msg = {\n+\t\t.dest_dev = ice_sbq_dev_phy_0,\n+\t\t.opcode = ice_sbq_msg_wr_p,\n+\t\t.msg_addr_low = lower_16_bits(addr),\n+\t\t.msg_addr_high = upper_16_bits(addr),\n+\t\t.data = val\n+\t};\n \tint err;\n \n-\tmsg.msg_addr_low = lower_16_bits(addr);\n-\tmsg.msg_addr_high = upper_16_bits(addr);\n-\tmsg.opcode = ice_sbq_msg_wr;\n-\tmsg.dest_dev = ice_sbq_dev_phy_0;\n-\tmsg.data = val;\n-\n \terr = ice_sbq_rw_reg(hw, &msg, LIBIE_AQ_FLAG_RD);\n \tif (err) {\n \t\tice_debug(hw, ICE_DBG_PTP, \"Failed to send message to PHY, err %d\\n\",\ndiff --git a/drivers/net/ethernet/intel/ice/ice_sbq_cmd.h b/drivers/net/ethernet/intel/ice/ice_sbq_cmd.h\nindex 21bb861febbf..86a143ebf089 100644\n--- a/drivers/net/ethernet/intel/ice/ice_sbq_cmd.h\n+++ b/drivers/net/ethernet/intel/ice/ice_sbq_cmd.h\n@@ -54,8 +54,9 @@ enum ice_sbq_dev_id {\n };\n \n enum ice_sbq_msg_opcode {\n-\tice_sbq_msg_rd\t= 0x00,\n-\tice_sbq_msg_wr\t= 0x01\n+\tice_sbq_msg_rd\t\t= 0x00,\n+\tice_sbq_msg_wr_p\t= 0x01,\n+\tice_sbq_msg_wr_np\t= 0x02,\n };\n \n #define ICE_SBQ_MSG_FLAGS\t0x40\n","prefixes":["iwl-next"]}